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Method for erasing split gate type flash memory

A split-gate flash memory and control gate technology, applied in the field of memory, can solve the problems of fast degradation speed of tunnel oxide layer and low flash memory durability, and achieve the effects of reducing voltage stress, slowing down degradation speed, and improving durability

Active Publication Date: 2013-10-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention solves the problems that the tunnel oxide layer in the flash memory degenerates quickly and the durability of the flash memory is low

Method used

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  • Method for erasing split gate type flash memory
  • Method for erasing split gate type flash memory
  • Method for erasing split gate type flash memory

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Embodiment Construction

[0022] As described in the background art, when the split-gate flash memory is erased, the tunnel oxide layer in the split-gate flash memory bears a large voltage stress, which causes degradation of the tunnel oxide layer, and thus Reduce the durability of the entire flash memory. After research, the inventor of the technical solution provided a method for erasing split-gate flash memory.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] figure 1 It is a schematic diagram of the cross-sectional structure of the split-gate flash memory according to the present invention. reference figure 1 , The split-gate flash memory includes: a semiconductor substrate 100 having a source region 200 and a drain region 300 spaced apart on the semiconductor substrate 100; a wor...

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Abstract

The invention discloses a method for erasing a split gate type flash memory. The split gate type flash memory comprises a first control gate, a second control gate, a source region, a drain region and a word line. The method comprises the following steps of: applying a first negative voltage to the first control gate and the second control gate at the time between a first moment and a second moment; applying a second negative voltage to the first control gate and the second control gate at the time between the second moment and a third moment, wherein an absolute value of the second negative voltage is more than that of the first negative voltage and the time between the second moment and the third moment accounts for 10%-20% of the time between the first moment and the third moment; applying a positive voltage to the word line and a 0V voltage to the source region and the drain region at the time between the first moment and the third moment. According to the method provided by the technical scheme of the invention, the degradation speed of a tunnel oxide layer in the split gate type flash memory can be reduced and the durability of the split gate type flash memory can be improved.

Description

Technical field [0001] The present invention relates to the technical field of memory, in particular to a method for erasing split-gate flash memory. Background technique [0002] Flash memory, as a kind of integrated circuit storage device, is widely used in portable computers, mobile phones, digital music players, etc. due to its high-speed, high-density, miniaturization, and data retention even after power failure. In electronic products. Generally, depending on the gate structure of the transistors constituting the memory cell, flash memory can be divided into two types: stacked-gate flash memory and split-gate flash memory. Among them, the split-gate flash memory has been widely used because it effectively avoids the over-erase effect and has a higher programming efficiency. [0003] The Chinese invention patent with the publication number CN101465161A provides a split-gate flash memory that shares a word line, and correspondingly provides a method for reading, programming a...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/14
Inventor 顾靖
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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