[0048] As described in the background art, the device performance of the fin-type FET in the prior art has problems.
[0049] After research, the inventor found that one of the reasons for the problem with the device performance of the fin-type FET in the prior art is that an etching process is used to form a support part, and a side wall is formed on the sidewall of the support part, and then the sidewall The wall is a mask to etch the hard mask layer and semiconductor substrate. When the fin is formed, the sidewall of the support portion is etched by the etching gas, and the sidewall of the support portion formed is uneven. When the support part is used as a support to form the side wall, the side wall formed close to the support part also has unevenness, and when the support part is subsequently removed, the side wall near the support part is still uneven, even due to etching There is a difference in the concentration of gas between the concave and the convex, which may further aggravate the unevenness of the side wall near the support part. The surface roughness of the formed side wall is large, which affects the accuracy of the subsequent fins. And the quality makes the device performance of the fin-type field effect tube poor.
[0050] Further, after research, the inventor found that although the side walls of the support part are uneven, which will affect the surface roughness of the side walls, if a material with good flattening characteristics is used to form the flowable layer on the side wall of the support part, After the support part is removed, an annealing process is assisted to process the flowable layer, which greatly improves the unevenness of the sidewalls formed by the flowable layer, and reduces the surface roughness of the sidewalls. Fins with higher accuracy and quality can also be obtained, and the formed fin-type FET has good device performance.
[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0052] Please refer to figure 2 , The method of forming a semiconductor device according to an embodiment of the present invention includes:
[0053] Step S201, providing a semiconductor substrate, the surface of the semiconductor substrate has a supporting portion;
[0054] Step S203, forming a flowable layer on the side wall of the supporting portion;
[0055] Step S205, after forming the flowable layer, remove the support part;
[0056] Step S207, after removing the supporting part, the flowable layer is processed to form a side wall with a flat side wall.
[0057] Specifically, please refer to Figure 3-Figure 12 , Figure 3-Figure 9 Shows a schematic cross-sectional structure diagram of a semiconductor device forming process according to an embodiment of the present invention, Figure 10-12 It shows an enlarged schematic top view of the position A during the formation of the semiconductor device of the embodiment of the present invention.
[0058] Please refer to image 3 , A semiconductor substrate 300 is provided, the surface of the semiconductor substrate 300 is covered with a hard mask film 301, and the surface of the hard mask film 301 has a supporting portion 303.
[0059] The semiconductor substrate 300 is used to provide a working platform for subsequent processes, and the material of the semiconductor substrate 300 is a silicon substrate or silicon on insulator (SOI). In an embodiment of the present invention, the semiconductor substrate 300 is single crystal silicon.
[0060] The hard mask film 301 is used to subsequently form a hard mask layer, and subsequently use the hard mask layer as a mask to etch the semiconductor substrate to form fins. The formation process of the hard mask film 301 is a deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. The hard mask film 301 is formed of a flowable film, such as borophosphosilicate glass, borosilicate glass, phosphosilicate glass, polyethylene silicon oxide or polyethylene silicon nitride, or ethyl orthosilicate and Ozone is formed.
[0061] In the embodiment of the present invention, the hard mask film 301 is formed using a low pressure chemical vapor deposition process (LPCVD), and the reactants used in the low pressure chemical vapor deposition process are ethyl orthosilicate and ozone. Since the tetraethyl orthosilicate and ozone are flowable materials, they have good planarization characteristics, and the formed hard mask film 301 has a flat surface.
[0062] It should be noted that in other embodiments of the present invention, the method for forming the hard mask film 301 may also be spin-on-dielectric (SOD), in which a liquid source is spin-coated on the surface of the semiconductor substrate 300.
[0063] The supporting portion 303 is located on the surface of the hard mask film 301 and is used for subsequent support when forming sidewalls. The forming steps of the supporting portion 303 are: forming a supporting film (not shown) covering the hard mask film 301; forming a photoresist layer (not shown) on the surface of the supporting film, the photolithography The adhesive layer covers a part of the supporting film; the supporting film is etched using the photoresist layer as a mask to form a supporting portion 303.
[0064] The material of the support portion 303 is silicon nitride, silicon oxynitride, silicon oxide or phosphosilicate glass. In order to facilitate the subsequent etching process, the material of the support portion 303 is different from the material of the hard mask film 301. In the embodiment of the present invention, the material of the supporting portion 303 is silicon nitride.
[0065] It should be noted that when the support film is etched using the photoresist layer as a mask, the sidewall of the support portion 303 is etched by the etching gas, and the formed support portion 303 has uneven sidewalls.
[0066] Please refer to Figure 4 with 10 , Picture 10 for Figure 4 The enlarged top view of center A. A flowable layer 305 located on the side wall of the supporting portion 303 is formed.
[0067] Taking into account the uneven sidewalls of the supporting portion 303, if the sidewalls are directly formed of silicon oxide, silicon oxynitride and other materials, the sidewalls of the sidewalls close to the supporting portion 303 will also be uneven, and then the uneven sidewalls When the hard mask film 301 and the semiconductor substrate 300 are etched for the mask, there will be a large deviation, which makes the size of the fin actually formed differ greatly from the ideal size, which affects the accuracy of fin formation and the accuracy of the fin. Quality, resulting in poor device performance of the final fin-type FET.
[0068] After research, the inventor found that although the side walls of the support part 303 are uneven, which will affect the surface roughness of the side walls, if a material with good flattening characteristics is used to form the flowable layer 305 on the side wall of the support part 303, After the support part 303 is removed, the flowable layer 305 is processed with the aid of an annealing process, which greatly improves the unevenness of the side wall formed by the flowable layer 305, and reduces the surface roughness of the side wall. It is small, and fins with higher accuracy and quality can be obtained later, and the formed fin-type FET has good device performance.
[0069] The flowable layer 305 is used to subsequently form sidewalls with flat sidewalls. Since the flowable layer 305 has good planarization characteristics, although the sidewalls of the supporting portion 303 are uneven, the sidewalls of the formed flowable layer 305 are still relatively flat. The forming step of the flowable layer 305 includes: forming a flowable film (not shown) covering the top and sidewalls of the semiconductor substrate 300 and the supporting portion 303; etching the flowable film until the supporting portion is exposed 303 and the semiconductor substrate 300.
[0070] Wherein, the process of etching the flowable film is an anisotropic dry etching process, which will not be repeated here.
[0071] Please refer to Figure 5 with Picture 11 , Picture 11 for Figure 5 The enlarged top view of center A. After the flowable layer 305 is formed, the supporting portion 303 is removed ( Figure 4 Shown).
[0072] The support portion 303 is removed to expose the sidewalls of the flowable layer 305 and the surface of the hard mask film 301 to facilitate subsequent processing of the flowable layer 305.
[0073] The process for removing the support portion 303 is an etching process, such as an anisotropic dry etching process. Since the process of removing the supporting portion 303 is well known to those skilled in the art, it will not be repeated here.
[0074] Please refer to Image 6 with Picture 12 , Picture 12 for Image 6 The enlarged top view of center A. Remove the support part 303 ( Figure 4 After the flowable layer 305 ( Figure 5 (Shown) is processed to form side walls 305a with flat side walls.
[0075] The flowable layer 305 is processed to form sidewalls 305a with flat sidewalls, which are used to subsequently use the sidewalls 305a as a mask to form fins with high accuracy and good quality.
[0076] The method for processing the flowable layer 305 is: annealing, UV light or plasma treatment. The gas used for processing the flowable layer 305 includes oxygen, which is mainly used to oxidize the flowable layer to form non-flowable silicon oxide. In addition, since the flowable layer 305 has good planarization characteristics, after the above-mentioned treatment is performed on the flowable layer 305, the sidewalls of the side walls 305a formed are flatter.
[0077] In the embodiment of the present invention, the method for processing the flowable layer 305 is annealing. The gas used in the annealing treatment includes nitrogen, argon, or helium in addition to oxygen, and its process parameters include: annealing temperature 400-600° C., annealing time 3-5 minutes. The sidewalls of the sidewall spacer 305a formed within this process parameter range are flatter.
[0078] Please refer to Figure 7 , Using the side wall 305a as a mask to etch the hard mask film 301 ( image 3 As shown), a hard mask layer 301a is formed.
[0079] The hard mask layer 301a is used as a subsequent mask to etch the semiconductor substrate 300 to form fins. The material of the hard mask layer 301a is the same as the material of the hard mask film 301. In an embodiment of the present invention, the hard mask layer 301a is formed of a flowable material, such as borophosphosilicate glass, borosilicate glass, phosphosilicate glass, polyethylene silicon oxide or polyethylene silicon nitride, or orthosilicic acid. Ethyl and ozone. Since the etching process for forming the hard mask layer 301a is well known to those skilled in the art, it will not be repeated here.
[0080] Please refer to Picture 8 , Remove the side wall 305a, and process the hard mask layer 301a to make the sidewall of the hard mask layer 301a flat.
[0081] The method for processing the hard mask layer 301a to flatten its sidewalls is annealing processing, ultraviolet light processing or plasma processing. In the embodiment of the present invention, oxygen, and nitrogen, argon, or helium are introduced to anneal the hard mask layer 301a. For details, please refer to the method of processing the flowable layer to form sidewalls, here No longer.
[0082] It should be noted that, in other embodiments of the present invention, after removing the support portion, the flowable layer may be used as a mask to etch the hard mask film to form a hard mask layer; then in the same process step The flowable layer and the hard mask layer are processed to form sidewalls with flat sidewalls and a hard mask layer with flat sidewalls; then, the semiconductor substrate is formed by etching the semiconductor substrate with the hard mask layer as a mask Fins.
[0083] Please continue to refer Picture 8 , Using the processed hard mask layer 301a as a mask to etch the semiconductor substrate 300 ( image 3 As shown), a fin 307 is formed, and the fin 307 is located on the surface of the etched semiconductor substrate 300a.
[0084] The fin 307 is formed by etching the semiconductor substrate. In the embodiment of the present invention, the sidewalls of the sidewalls formed are flat, and the sidewalls of the hard mask layer 301a formed using the sidewalls as a mask are also relatively flat, so the fins 307 formed along the semiconductor liner The dimension in the surface direction of the bottom 300 is not much different from the width of the sidewall and the width of the hard mask layer 301a, which facilitates the formation of a fin 307 with high dimensional accuracy, and is protected by the hard mask layer 301a to form the fin 307 The quality is good.
[0085] It should be noted that the process of etching the semiconductor substrate is well known to those skilled in the art, and will not be repeated here.
[0086] Please refer to Picture 9 , The hard mask layer is removed, and the top of the fin 307 is exposed.
[0087] The hard mask layer is removed to facilitate subsequent formation of fin-type field effect transistors. The process of removing the hard mask layer is well known to those skilled in the art, and will not be repeated here.
[0088] After the above steps are completed, the semiconductor device of the embodiment of the present invention is completed.
[0089] Correspondingly, please refer to Figure 13 , The inventor also provides a method for forming a fin-type FET, including:
[0090] Step S401, providing a semiconductor substrate, the surface of the semiconductor substrate has a supporting portion;
[0091] Step S403, forming a flowable layer on the side wall of the supporting part;
[0092] Step S405, after forming the flowable layer, remove the support part;
[0093] Step S407, after removing the supporting part, process the flowable layer to form side walls with flat side walls;
[0094] Step S409, using the sidewall spacers of the semiconductor device as a mask to etch the semiconductor substrate to form fins;
[0095] Step S411, removing the side wall to expose the top of the fin;
[0096] Step S413, forming a gate structure located on the surface of the etched semiconductor substrate and straddling the top and sidewalls of the fin;
[0097] Step S415, using the gate structure as a mask, doping the fins to form source/drain regions.
[0098] For step S401 to step S411, please refer to the detailed description in the method of forming a semiconductor device, which will not be repeated here.
[0099] The gate structure is used to form the gate of the fin-type FET, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and straddling the top and sidewalls of the fin; The gate electrode layer of the gate dielectric layer. The material of the gate dielectric layer is silicon oxide or high-K dielectric; the material of the gate electrode layer is polysilicon or metal.
[0100] The source/drain regions are used for subsequent source/drain formation. The source/drain region is formed by doping the fins on both sides of the gate structure with ions as a mask. Since the ion doping process is well known to those skilled in the art, it will not be repeated here.
[0101] After the above steps are completed, the fabrication of the fin field effect transistor of the embodiment of the present invention is completed. Since the sidewalls of the sidewalls formed by the forming method of the embodiment of the present invention are relatively flat, the dimensions of the subsequently formed fins along the surface of the semiconductor substrate have high accuracy, and the gap between the actual formed size and the ideal size is small. The forming process is simple. Moreover, when the sidewalls with flat sidewalls are used as a mask, a hard mask layer with flat sidewalls is formed first, and then when the hard mask layer with flat sidewalls is used as a mask to form the fins, the fins are not only along The accuracy of the dimension in the surface direction of the semiconductor substrate is high, and the quality of the formed fin is good, and the performance of the formed fin-type field effect transistor is stable.
[0102] In summary, firstly, a flowable layer with good covering flatness is formed on the side wall of the support portion, and then the flowable layer is processed subsequently to form a side wall with a flat side wall. The side wall with a flat side wall is subsequently When used as a mask to form various component parts of a semiconductor device, the component parts with higher accuracy can be obtained, and the performance of the formed semiconductor device is stable.
[0103] Further, it also includes: a hard mask film formed of a flowable material, etching the hard mask film with a sidewall with flat sidewalls as a mask, and performing corresponding treatments to form a hard mask with flat sidewalls When the film layer is etched using the hard mask layer with flat sidewalls as a mask to form various components of the semiconductor device, the components with higher accuracy can be obtained, and the quality of the components is good , The performance of the formed semiconductor device is stable.
[0104] With the fin-type FET formed by the above method, since the sidewalls of the sidewalls formed are relatively flat, the size of the subsequently formed fin along the surface of the semiconductor substrate has high accuracy, and the actual size is different from the ideal size. Small and simple forming process. Moreover, when the sidewalls with flat sidewalls are used as a mask, a hard mask layer with flat sidewalls is formed first, and then when the hard mask layer with flat sidewalls is used as a mask to form the fins, the fins are not only along The accuracy of the dimension in the surface direction of the semiconductor substrate is high, and the quality of the formed fin is good, and the performance of the formed fin-type field effect transistor is stable.
[0105] Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and technical content disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solution makes possible changes and modifications. Therefore, all simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention belong to the technical solution of the present invention. protected range.
