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Addressing method, device and system

An addressing and addressing module technology, applied in the addressing field, can solve problems such as frequent setting of BSR, and achieve the effect of improving instruction execution efficiency and data transmission efficiency

Active Publication Date: 2016-04-13
SHANGHAI EASTSOFT MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides an addressing method, device and system to solve the problem that BSR needs to be frequently set for direct addressing during data transmission processing between different BANKs in the unified addressing scheme in the prior art

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  • Addressing method, device and system

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Embodiment Construction

[0031] In order to give a clear and detailed introduction to the embodiments of the present invention, the direct addressing and indirect addressing under the two addressing schemes in the prior art are introduced first.

[0032] 1) Interleaved addressing

[0033] Suppose the data storage space is 2 10 =1024 bytes, the address range is 000H~3FFH, wherein the storage space of GPR is 768 bytes, and the storage space of SFR is 256 bytes. The addressing instruction bit width of the microprocessor is 16 bits, including 9-bit instruction code and 7-bit operand. The data storage space is divided into 8 BANKs, each BANK is 128 bytes, and the lower 32 addresses in a BANK Assigned to SFR, the upper 96 addresses are assigned to GPR.

[0034] figure 2 Schematic diagram of address mapping for interleaved addressing data storage space when directly addressing. Such as figure 2 As shown, in direct addressing, the mapped BANK is selected through the BSR, and the addressing instruction ...

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Abstract

The invention provides an addressing method, device and system. The addressing method comprises the steps of obtaining an addressing instruction; confirming a selected first physical address subspace according to a first BSR set value; establishing mapping relation of the selected first physical address subspace and a first logic address subspace in a pre-established logic address space; confirming a logic address corresponding to the addressing instruction; confirming a physical address in the selected first physical address subspace corresponding to the logic address according to the mapping relation of the selected first physical address subspace and the first logic address subspace if the logic address is located in the first logic address subspace; confirming a physical address in a second physical address subspace corresponding to the logic address according to mapping relation of the pre-established physical address subspace and a second logic address subspace if the logic address is located in the first logic address subspace of a pre-established physical address space.

Description

technical field [0001] The present invention relates to addressing technology, in particular to an addressing method, device and system. Background technique [0002] The application of microprocessors is becoming more and more extensive, and the demand for data storage space is also increasing. However, due to the limitation of the instruction bit width of the microprocessor, the addressing range of the addressing instruction to the data storage space is limited. Now, the addressing range of addressing instructions can no longer cover the entire data storage space, and can only address part of the area. For example, a data storage space of 2 10 =1024 bytes, address range 000H~3FFH, the addressing instruction bit width of the microprocessor is 16 bits, including 9-bit instruction code and 7-bit operand, wherein, the 7-bit operand represents the address information of addressing, addressing Range is 2 7 = 128 bytes. figure 1 It is a schematic diagram of a 16-bit addressi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G06F9/30
Inventor 史卫东崔炳磊潘松许海迎
Owner SHANGHAI EASTSOFT MICROELECTRONICS