Adaptive conduction time generation circuit applied in dc-dc converter
A DC-DC, on-time technology, used in analog integrated circuits, DC-DC converters, and adaptive on-time generation circuits, can solve problems such as weak transient response capabilities, and achieve good transient response capabilities, The effect of avoiding electromagnetic interference
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Embodiment 1
[0022] refer to figure 2 , The adaptive on-time generation circuit of the present invention includes: an input voltage sampling unit 1 , an output voltage and current sampling compensation unit 2 and a comparison and time logic generation unit 3 .
[0023] The input voltage sampling unit 1 is provided with three input terminals a, b, c and an output terminal d; wherein the first input terminal a and the second input terminal b are respectively connected to the input voltage V of the DC-DC converter IN and DC-DC converter internal reference voltage V R , for the DC-DC converter input voltage V IN Sampling; the third input terminal c is connected with the pulse inverse signal output by the time logic generation unit 3 ;Output d output voltage signal V C To compare and time logic generation unit 3, the voltage signal V C proportional to the DC-DC converter input voltage V IN and the conduction time of the main switch in the DC-DC converter.
[0024] The output voltage and...
Embodiment 2
[0070] The output voltage and current sampling compensation unit 2 and the comparison and time logic generation unit 3 of the present invention are the same as those in the first embodiment.
[0071] refer to Figure 5 , the input voltage sampling unit 1 of the present invention comprises: operational amplifier 401, 2 PMOS transistors M 401 , M 402 , 2 NMOS tubes M 404 , M 405 , the third capacitor C 3 and 3 resistors, the tenth resistor R 10 , Eleventh resistance R 11 and the twelfth resistor R 12 ;
[0072] The eleventh resistor R 11 with the twelfth resistor R 12 in series, across the DC-DC converter’s input voltage V IN between the ground;
[0073] The operational amplifier 401, its non-inverting input terminal is connected to the eleventh resistor R 11 with the twelfth resistor R 12 The common end; its inverting input and NMOS tube M 404 The source is connected; its output is connected to the NMOS tube M 404 grid;
[0074] The NMOS tube M 404 , its drain ...
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