Semiconductor memory device
A memory and semiconductor technology, applied in the fields of semiconductor devices, static memory, digital memory information, etc., can solve the problems of reduced memory cell occupancy, inability to give full play to the advantages of three-dimensional structure, and increased current consumption.
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no. 1 example
[0032]
[0033] figure 1 is a diagram showing the structure of the semiconductor memory device according to the first embodiment. The semiconductor memory device includes a memory cell array 1 . The memory cell array 1 includes a plurality of stacked memory cell mats (memory cell layers). Each memory cell mat (mat) includes a plurality of bit lines BL (first line) and a plurality of word lines WL (second line), and a memory cell MC selected by these word lines WL and bit lines BL.
[0034] The bit line BL in the memory cell pad is electrically connected to the column control circuit 2, which can control the bit line BL by operation and perform erasure of data in the memory cell MC, writing of data in the memory cell MC and from the memory cell MC. Reading data from a memory cell MC (hereinafter, erasing data in a memory cell MC and writing data to a memory cell MC are collectively referred to as a "write operation", and reading data from a memory cell MC is referred to as ...
no. 2 example
[0088] The first embodiment describes access to one memory cell MC, while the second embodiment describes access to a plurality of memory cells MC at the same time.
[0089] A simultaneous read operation on multiple memory cells is described first.
[0090] Figure 3A and 3BThe shown asymmetric variable resistance memory cell (memory cell MC) changes its characteristics when a large amount of current continues to flow into it. Therefore, for the bit line BL used to monitor the cell current, one memory cell needs to be selected on each line to monitor and control the cell current at each memory cell MC.
[0091] Therefore, in this embodiment, when accessing a plurality of memory cells MC at the same time, only one word line WL is selected and a plurality of bit lines BL are selected by performing. The distance between the selected word line WL and the word line driver 3' is shortened to select as many bit lines BL as possible within the allowable current of the selected word...
no. 3 example
[0108] The third embodiment describes a method of sequentially reading data from different memory cells. Hereinafter, the read operation by this method is referred to as "sequential read operation".
[0109] Continuous read operation method can be considered from two aspects. The first is a method of fixing a selected word line and sequentially switching and selecting among bit lines in each access cycle. The second is a method of fixing the selected bit line and sequentially switching and selecting among the word lines in each access cycle. Among these methods, the second one is more advantageous in the instance of floating access method.
[0110] Figure 15 is a diagram showing consecutive read operations in the semiconductor memory device according to the present embodiment. Figure 16 is a graph showing a change in voltage on a bit line when the floating access method of this embodiment is used for one access to a memory cell.
[0111] In the read operation, as descri...
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