Space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction

A space management and integrated circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of long running time and low operating efficiency

Active Publication Date: 2013-12-25
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this generation method is inefficient to run, especially when dealing with large-scale interconnect structures, and the running time is too long

Method used

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  • Space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction
  • Space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction
  • Space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction

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Embodiment Construction

[0019] Concrete invention point is as follows:

[0020] 1) Define the upper limit of the distance from a point in a three-dimensional unit (hereinafter also referred to as “unit”) to the nearest conductor, which is called the unit’s shortest distance threshold. When checking the positional relationship between a conductor and a unit to determine whether the conductor is inserted into the candidate conductor list, the shortest distance threshold is used for screening. Specifically, if the distance from the conductor to the unit is greater than or equal to the shortest distance threshold, the conductor must not be inserted into the candidate conductor list. Otherwise, other judgments are made to determine whether the conductor should be inserted into the candidate conductor list. Once a conductor is inserted into the candidate conductor list, it is necessary to determine whether the sum of the distance from the conductor to the unit and the length of the longest side of the uni...

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Abstract

The invention provides a space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction. The method includes the following steps: initializing a root node of an octree of an integrated-circuit three-dimensional simulation space; retaking a conductor B from an integrated circuit interconnection structure; starting from the root node, performing depth-first traversal on the octree; acquiring a next traversed node T corresponding to a three-dimensional unit T in the integrated-circuit three-dimensional simulation space; when the node T is a leaf node, judging whether the conductor B should be inserted into a candidate conductor list of the three-dimensional unit T or not according to a preset minimum distance threshold L(T); updating the minimum distance threshold L(T). After all the conductors are inserted into the candidate conductor list, space management data required for the integrated circuit interconnection capacitance parameter extraction are acquired. By the method, generation time for the space management data can be shortened greatly, so that capacitance parameter extraction can be performed on the large-scale integrated circuit interconnection structure.

Description

technical field [0001] The invention relates to the field of physical design of VLSI (Very Large Scale Integrated circuits, VLSI), in particular to the extraction of capacitance parameters of integrated circuit interconnections. Background technique [0002] In the design process of integrated circuits, the functional description must first be proposed, and then the layout describing the size and structure of the semiconductor process is obtained through logic design and layout design, and finally layout verification is performed, that is, computer software simulation is used to verify whether the above design meets the requirements. If the requirements are met, proceed to the next step of manufacturing. Otherwise, if the requirements are not met, return to logic design and layout design for necessary corrections. In layout verification, an important link is "interconnection parasitic parameter extraction". [0003] With the development of integrated circuit manufacturing ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 喻文健张超
Owner TSINGHUA UNIV
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