Fin field effect transistor and method of forming the same

Abstract

A fin-type field effect transistor and a method for forming the same, wherein the method for forming a fin-type field effect transistor of the present invention includes: providing a semiconductor substrate, the surface of the semiconductor substrate is covered with an insulating layer, which penetrates the thickness of the insulating layer and is connected with the insulating layer. A first sub-fin with a flush surface, an epitaxial intrinsic layer located on the surface of the first sub-fin, wherein the first sub-fin has doping ions, and the epitaxial intrinsic layer does not have doping ions; An isolation layer is formed on the surface of the layer, and the isolation layer has an opening that defines a gate structure; the epitaxial intrinsic layer in the opening is trimmed, and the trimmed epitaxial intrinsic layer is doped; an epitaxial layer is formed in the opening layer, the epitaxial layer uniformly covers the top and sidewalls of the doped epitaxial intrinsic layer; a gate structure spanning the top and sidewalls of the epitaxial layer is formed in the opening. The formed fin-type field effect transistor has low threshold voltage, small gate leakage current and stable device performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a fin field effect transistor and a forming method thereof. Background technique [0002] Fin field effect transistor (Fin FET) is a common multi-gate device, figure 1 A schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art is shown. Such as figure 1 As shown, it includes: a semiconductor substrate 10, on which a protruding fin 14 is formed, and the fin 14 is generally obtained by etching the semiconductor substrate 10; a dielectric layer 11 covering the The surface of the semiconductor substrate 10 and a part of the sidewall of the fin 14; the gate structure 12 spans the fin 14 and covers the top and sidewall of the fin 14, and the gate structure 12 includes a gate dielectric layer (not shown in the figure) and the gate electrode (not shown in the figure) on the gate dielectric layer. For the Fin FET, the top...

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Problems solved by technology

[0003] However, as the process node is further reduced, there are problems with the device performance of the prior art FinFET

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