Mapping method and device for simulating single physical network port into multiple logical network ports

Abstract

The embodiment of the invention relates to a mapping method and a device for simulating a single physical network port into multiple logical network ports. The method comprises the steps of simulating and mapping the single physical network port into the logical network ports through time division multiplexing, assigning original MAC (Media Access Control) address information, first port identification information and a transmission time slot to the mapped logical network ports, determining a mapping relationship between the logical network ports and the physical network port through the original MAC address information or the first port identification information and the transmission time slot, and further receiving a data packet transmitted by external communication equipment or transmitting the data packet to external network equipment. The method and the device solve the bottle neck that the high-speed data packet cannot be received or transmitted through the single physical network port in the prior art, and realize the support of the single physical network port to the high-speed 10-gigabit Ethernet.

Description

technical field [0001] The invention relates to network interface technology, in particular to a mapping method and device for simulating a single physical network port into a plurality of logical network ports. Background technique [0002] On-chip multi-core processors (Chip Multi Processors, referred to as: CMP) integrate multiple computing cores into one chip processor chip, thereby improving the computing power of the processor. Usually, a high-performance network processor uses a multi-core processor and adopts a multi-core parallel processor structure. The on-chip processor is roughly divided into a core processor and a forwarding engine according to tasks. The core processor has a dedicated hardware coprocessor, and uses dedicated hardware to implement general-purpose functional modules that require high-speed processing to improve system performance. The forwarding engine usually uses a dedicated reduced instruction set and is optimized for network protocol process...

AI Technical Summary

Problems solved by technology

[0004] However, since the core processor in the network processor has a dedicated hardware coprocessor, the performance of the coprocessor will affect the overall performance of the network processor (if the coprocessor has a performance bottleneck, it will directly lead to the performance bottleneck of the network processor)

When using a coprocessor for data transmission, the single-channel data transmission rate of the coprocessor cannot match the rate of the high-speed network 10 Gigabit Ethernet. If the single-channel transmission method is used, the performance bottleneck of the coprocessor will cause network The performance bottleneck of the core processor in the processor

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