Mapping method and device for simulating single physical network port into multiple logical network ports

A technology of a logical network port and a mapping device, which is applied in the field of network interfaces and can solve problems such as network processor performance bottlenecks, core processor performance bottlenecks, and coprocessor performance bottlenecks.

Inactive Publication Date: 2014-01-22
INST OF ACOUSTICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, since the core processor in the network processor has a dedicated hardware coprocessor, the performance of the coprocessor will affect the overall performance of the network processor (if the coprocessor has a performance bottleneck, it will directly lead to the performance bottleneck of the network processor)
When using a cop

Method used

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  • Mapping method and device for simulating single physical network port into multiple logical network ports
  • Mapping method and device for simulating single physical network port into multiple logical network ports
  • Mapping method and device for simulating single physical network port into multiple logical network ports

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Embodiment 1

[0059] Below to figure 1 As an example, describe in detail the mapping method in which a single physical network port is simulated as multiple logical network ports provided by Embodiment 1 of the present invention. figure 1 The flow chart of the mapping method for simulating a single physical network port into multiple logical network ports is provided in Embodiment 1 of the present invention. In the embodiment of the present invention, the implementer who performs the following steps may be a network server, but it is not limited thereto , and the following takes the network server as the implementation subject to describe in detail. Such as figure 1 As shown, this embodiment specifically includes the following steps:

[0060] Step 110, simulating a single physical network port into multiple logical network ports through time division multiplexing.

[0061] Specifically, the network server includes a single physical network port, and the physical network port is used to r...

Embodiment 2

[0073] In the foregoing embodiments, it is briefly described that the network server can determine the mapping relationship between multiple logical network ports and physical network ports through the original MAC address information, and then receive the data packets sent by the external communication device. In order to facilitate real-time understanding of the present invention, the following will further explain and illustrate with specific embodiments in conjunction with the accompanying drawings, and the embodiments do not constitute a limitation to the embodiments of the present invention.

[0074] Below to figure 2 As an example to describe in detail the working process of the network server receiving data packets provided by the second embodiment of the present invention, figure 2 The flow chart of receiving data packets provided by Embodiment 2 of the present invention. In the embodiment of the present invention, the implementer who executes the following steps ma...

Embodiment 3

[0087] In the foregoing embodiments, it is briefly described that the network server can determine the mapping relationship between multiple logical network ports and physical network ports through the first port identification information and the sending time slot, and then send data packets to external network devices. In order to facilitate real-time understanding of the present invention, the following will further explain and illustrate with specific embodiments in conjunction with the accompanying drawings, and the embodiments do not constitute a limitation to the embodiments of the present invention.

[0088] Below to image 3 As an example, the working process of sending data packets by the network server provided by the third embodiment of the present invention is described in detail. image 3 The flow chart of sending data packets provided by Embodiment 3 of the present invention. In the embodiment of the present invention, the implementer who executes the following ...

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Abstract

The embodiment of the invention relates to a mapping method and a device for simulating a single physical network port into multiple logical network ports. The method comprises the steps of simulating and mapping the single physical network port into the logical network ports through time division multiplexing, assigning original MAC (Media Access Control) address information, first port identification information and a transmission time slot to the mapped logical network ports, determining a mapping relationship between the logical network ports and the physical network port through the original MAC address information or the first port identification information and the transmission time slot, and further receiving a data packet transmitted by external communication equipment or transmitting the data packet to external network equipment. The method and the device solve the bottle neck that the high-speed data packet cannot be received or transmitted through the single physical network port in the prior art, and realize the support of the single physical network port to the high-speed 10-gigabit Ethernet.

Description

technical field [0001] The invention relates to network interface technology, in particular to a mapping method and device for simulating a single physical network port into a plurality of logical network ports. Background technique [0002] On-chip multi-core processors (Chip Multi Processors, referred to as: CMP) integrate multiple computing cores into one chip processor chip, thereby improving the computing power of the processor. Usually, a high-performance network processor uses a multi-core processor and adopts a multi-core parallel processor structure. The on-chip processor is roughly divided into a core processor and a forwarding engine according to tasks. The core processor has a dedicated hardware coprocessor, and uses dedicated hardware to implement general-purpose functional modules that require high-speed processing to improve system performance. The forwarding engine usually uses a dedicated reduced instruction set and is optimized for network protocol process...

Claims

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Application Information

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IPC IPC(8): H04L29/10
Inventor 张武郭晓东王劲林郭秀岩
Owner INST OF ACOUSTICS CHINESE ACAD OF SCI
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