Universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core

Abstract

The invention discloses a universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core, which comprises an in-situ operation unit, a base-2 pipeline type butterfly operation unit and a result processing unit, wherein the in-situ operation unit is used for segmenting and sorting input digital signals, completing in-situ operation by means of address order reversal, sequentially caching the input digital signals in a way of keeping 256 points in each group by using a ping-pang cache method, and generating data which are convenient for butterfly operation input via screening of odd and even sequences; the base-2 pipeline type butterfly operation unit comprises multiple stages of butterfly pipeline operation units; a first-stage butterfly pipeline operation unit is used for receiving data generated by the in-situ operation unit, and then each stage of butterfly pipeline operation unit is connected with a previous stage butterfly pipeline operation unit respectively to calculate FFT operation output corresponding to the input of each point; the result processing unit is connected with the base-2 pipeline type butterfly operation unit, and is used for sorting the FFT operation output calculated by using the base-2 pipeline type butterfly operation unit.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a general-purpose floating-point full-pipeline FFT operation IP core. [0002] Background technique [0003] FFT (Fast Fourier Transform, Fast Fourier Transform) operation is an important digital signal transformation algorithm in digital signal processing, which is powerful and widely used. Limited to the FPGA technology and integration level, most FPGA implementations of FFT operations are fixed-point or block floating-point. In addition to expensive authorization and cumbersome configuration, the IP cores of floating-point FFT operations using these two methods also have the following problems: Point defect: [0004] 1. The precision is low, and the calculation process using fixed-point or block floating-point methods will produce serious accumulated errors, which may cause large distortion to the final FFT result; [0005] 2. The range of signal represent...

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Problems solved by technology

[0006] 3. Poor real-time performance, the FFT processing architecture is not optimized enough, and full pipeline operation is not realized. Each FFT operation has to wait until the end of the previous FFT operation to start the operation process again, and the real-time performance is poor;

[0007] 4. The basic multiply-add operator has defects. The fixed-point multiply-adder lacks accuracy guarantee due to the fixed-point number operation. The IP core of the floating-point multiply-adder has an excessively long operation pipeline level, which greatly prolongs the calculation time of FFT through the superposition effect.

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