Integrated semiconductor device and wafer level method of fabricating the same

Abstract

The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via ("TSV") extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. The invention further provides an integrated semiconductor device and a wafer level method of fabricating the same.

Description

[0001] priority [0002] This patent claims priority to U.S. Patent Application No. 61 / 677,902, filed July 31, 2012, entitled "INTEGRATED PASSIVE AND CMOS DEVICE AND WAFER LEVEL METHOD OF FABRICATING THE SAME," the entire contents of which are hereby incorporated by reference Reference. technical field [0003] The present invention generally relates to the field of semiconductor technology, and more particularly, to a stacked semiconductor device and a manufacturing method thereof. Background technique [0004] Passive electronic devices such as capacitors or inductors are sometimes integrated with complementary metal oxide semiconductor ("CMOS") chips. Typically, large passive components are necessary when large capacitance or inductance is required. As a result, these devices can only be interconnected by external electrical paths, such as wire bonds. Also, when working with larger chip sizes, longer electrical paths are required. [0005] Traditional passive devices / ...

AI Technical Summary

Problems solved by technology

First, electrical parasitics caused by longer electrical paths degrade chip performance, especially after molding

Second, it is difficult to reduce the size of the system due to the wire bonding of the passive components to the pads of the CMOS chip

Third, since the passive components must be independently bonded to the CMOS chip, the accuracy is reduced, further increasing the difficulty of system shrinking

Fourth, precise assembly of multiple passive components with CMOS chips is laborious, increasing manufacturing costs

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