Structure for improving breakdown voltages of high-voltage LDMOS device

Abstract

The invention discloses a structure for improving breakdown voltages of a high-voltage LDMOS device. The method includes the steps that a drift region which is composed of a deep trap is formed on a silicon substrate of the LDMOS device; a field oxide layer is formed in the deep trap, a buried layer is formed below the field oxide layer, a drain region polycrystal filed plate is formed on one side, close to a drain region, of the field oxide layer, and a grid electrode polycrystal filed plate is formed on the other side of the field oxide layer; a trap region is formed in the silicon substrate, a source region which is composed of a first doping region is formed in the trap region, and a drain region which is composed of a second doping region is formed in the deep trap; a source electrode is led out from the first doping region through a source region metal filed plate, and the drain region is connected with the drain region polycrystal filed plate through a drain region metal filed plate; a grid electrode metal filed plate is formed between the source region metal filed plate and the drain region metal filed plate; at least one field plate is further formed above the drift region. By the adoption of the structure, electric field distribution can be changed, the electric field intensity of the drift region is improved, meanwhile, the influence on the electric field intensity at the two ends of the source electrode and a drain electrode is small, the entire electric field integral area of the device is increased, and therefore the withstand voltage level of the high-voltage LDMOS device is effectively improved.

Description

technical field [0001] The invention relates to a structure of a semiconductor device, in particular to a structure and a method for improving the breakdown voltage of an ultra-high voltage LDMOS device. Background technique [0002] LDMOS devices such as figure 1 As shown, a P-type silicon substrate 1 is included, and an N-type deep well 2 is formed on the silicon substrate 1, and the N-type deep well 2 constitutes a drift region; a field oxide layer 4 is formed in the deep well 2, and the field oxide layer 4 below A P+ buried layer 5 is formed, and the buried layer 5 is not in contact with the field oxide layer 4 in the vertical direction. A drain region polycrystalline field plate 7 is formed on one side of the field oxide layer 4 close to the drain region, and a gate polycrystalline field plate 6 is formed on the other side of the field oxide layer 4 . A P-type well region 3 is formed in the silicon substrate 1, the well region 3 is drawn out from the third doped regio...

AI Technical Summary

Problems solved by technology

However, at the edge of the field plate, due to the concentration of the electric force lines, there will be an electric field peak. Compared with this, most of the area above the drift region does not have any field plate, and the electric field intensity is low, resulting in the peak electric field of the final device. Drain and source high, middle low

As we all know, the integral of the area under the electric field is the withstand voltage of the device, so the withstand voltage of the device is still limited

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