Chip clock signal generation circuit and chip system
A clock signal and circuit generation technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of increased chip cost and large occupied area
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
example 1
[0049] This example is used to illustrate the chip clock signal generating circuit 100 that provides a high-precision target clock signal for the chip, wherein the theoretical frequency of the basic clock signal CLK0 output by the basic clock signal generating module 101 is 800MHz±30% (here Assuming that the frequency deviation is +24%, the actual frequency of the basic clock signal CLK0 is 992MHz, which belongs to a high-frequency clock signal), the frequency of the target clock signal CLKS required inside the chip is 20MHz, and the frequency parameter storage module 102 is EEPROM, and the frequency parameter Reading and processing module 103 is the CPU inside the chip, and the initial frequency division factor of clock frequency division module 104 is 64, and frequency parameter writing module 105 is EEPROM data downloading circuit (such as Figure 4 shown).
[0050] After the chip clock signal generation circuit 100 is powered on, the basic clock signal generation module 10...
example 2
[0053] This example is used to illustrate the chip clock signal generation circuit 100 that provides high-precision timing digital signals outside the chip, wherein the theoretical frequency of the basic clock signal CLK0 output by the basic clock signal generation module 101 is 32MHz±30% (here Assuming that the frequency deviation is -27.5%, the actual frequency of the basic clock signal CLK0 is 23.2MHz, which belongs to a low-frequency clock signal), the frequency parameter storage module 102 is FLASH, the frequency parameter reading and processing module 103 and the frequency parameter writing module 105 Included in the FLASH controller inside the chip, the baud rate of the external target timing digital signal OCLKS output by the external timing digital signal generation module 107 is 9600bps (such as Figure 5 As shown), since the basic clock signal CLK0 is a low-frequency clock signal, the external clock frequency detection circuit 200 does not need to perform initial fre...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 