Nor Flash chip control method based on AXI bus

Abstract

The invention discloses a Nor Flash chip control method based on an AXI bus and belongs to the technical field of Flash chip control. The Nor Flash chip control method based on the AXI bus is realized through a system. The system comprises an AXI bus interface, a programmable device and a Nor Flash chip interface. The AXI bus interface is connected with the programmable device, the programmable device is connected with the Nor Flash chip interface, the AXI bus interface is connected with an SOC system, the Nor Flash chip interface is connected with a Nor Flash chip, the programmable device is used for receiving and processing information transmitted by the AXI bus and controlling reading and writing of the Nor Flash chip according to requirements, and then communication between the AXI bus and Nor Flash is achieved. According to the Nor Flash chip control method based on the AXI bus, due to the fact that the AXI bus is adopted, bridge connection between clock domains is simplified, and data processing capacity is greatly improved; meanwhile, due to the fact that the addresses of the AXI bus are separated from data channels, each channel can be optimized individually.

Description

technical field [0001] The invention relates to a method for controlling a Nor Flash chip based on an AXI bus, and belongs to the technical field of Flash chip control. Background technique [0002] At present, the application of SOC is becoming more and more popular. In order to meet the requirements of customers, the voice of stronger, faster and more functions is rising day by day. As an indispensable and crucial part of SOC - memory, high speed, small size, low cost and large capacity have become its main pursuit. In order to meet the high-speed requirements, not only must there be a more optimized Flash architecture, but also how to use the high-speed bus to access the Flash is also a crucial issue. [0003] The AXI bus is an on-chip bus for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, it supports unaligned data transmission, and in a burst transmission, only the first address is needed to start the transmission...

AI Technical Summary

Problems solved by technology

"Microelectronics and Computers" 2013 Issue 06 mentioned the design of the Nor Flash controller IP in the article "A Nor Flash Controller IP Design Compatible with AHB Bus" published by Tian Peng et al., in which the AHB bus used is relatively Complex, low data throughput, since the AHB bus address and data channels are not separated, it is difficult to optimize each channel individually

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