Synchronous sampling clock closed loop correcting method and system based on FPGA

Abstract

The invention discloses a synchronous sampling clock closed loop correcting method and system based on an FPGA. The method comprises the first step of respectively judging the pulse duration of a PPS pulse signal and the triggering period of adjacent pulses to detect the correctness of the pulse signal, the second step of receiving and detecting action signals sent by a PPS judging module in real time to make a corresponding response, the third step of correcting the frequency of a local crystal oscillator clock through an error correcting module and measuring and correcting the phase-position error of a synchronous repeated sampling signal according to the state of the action signals, and the fourth step of generating a synchronous repeated sampling signal through a frequency doubling calculating module, meanwhile, feeding an output signal back to the error correcting module to form a closed loop system, correcting information according to the corrected information and automatically adjusting the output. The method solves the problems that on the basis that data synchronous sampling based on a GPS is studied, and due to the fact that a merging unit synchronous sampling clock is highly dependent on a crystal oscillator, the output error is large under the situation that the crystal oscillator is aged and the frequency accuracy is lowered.

Description

technical field [0001] The invention belongs to the field of electrotechnical technology, and in particular relates to an FPGA-based closed-loop correction method for synchronous sampling clocks. Background technique [0002] The smart substation takes the digitalization of the whole station information, the networking of the communication platform, and the standardization of information sharing as the basic requirements, and realizes the functions of information collection, measurement, control, protection, monitoring and metering. The basis of the application function, it requires the electronic transformer to sample the data of the grid current and voltage thousands of times per second, and once sampled, it can be shared by various intelligent electronic devices (IEDs) in multiple smart substations. However, regardless of the calculation and processing of control, protection, or monitoring and measurement, the sampling data should be collected at the same time point to av...

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Problems solved by technology

[0005] In view of the above problems, the present invention proposes a design of the synchronous sampling clock in the merging unit of the electronic transformer, which is dedicated to solving the strong dependence of the synchronous sampling clock of the merging unit on the crystal oscillator. When the crystal oscillator is aging and the frequency accuracy is reduced, the output big error

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