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Reversible logic-based 4-bit array multiplier

A multiplier and logic technology, applied in the field of microelectronics, can solve the problem of high power consumption of devices and achieve the effect of reducing circuit delay

Active Publication Date: 2014-03-12
CHONGQING UNIV OF POSTS & TELECOMM
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  • Abstract
  • Description
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Problems solved by technology

[0005] For the deficiencies in the prior art, the purpose of the present invention is to provide a 4-bit array multiplier based on reversible logic gate design for the defects of high power consumption of devices in the digital circuits of the prior art

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Embodiment Construction

[0018] The specific implementation manner and working principle of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0019] Such as figure 1 As shown, a 4-bit array multiplier based on reversible logic is composed of a partial product generation module based on reversible logic and three 4-bit carry-skip adders based on reversible logic. The quantum cost is 329 ; The input end of the partial product generation module is used to input two groups of 4-bit binary numbers a 3 a 2 a 1 a 0 and b 3 b 2 b 1 b 0 , the output of the partial product generating module sequentially outputs 16 partial products P 33 P 23 P 13 P 03 ,P 32 P 22 P 12 P 02 ,P 31 P 21 P 11 P 01 ,P 30 P 20 P 10 P 00 , where P 00 As the lowest bit calculation result P 0 ; put P 30 P 20 P 10 Add a 0 and P 31 P 21 P 11 P 01 Corresponding to the A sent to the first carry skip adder respectively 3 A 2 A 1 A 0 and B 3 B 2...

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Abstract

The invention discloses a reversible logic-based 4-bit array multiplier. The reversible logic-based 4-bit array multiplier is formed by cascading a reversible logic-based partial product generation module and three reversible logic-based 4-bit carry skip adders in layers, wherein the input port of the multiplier inputs two groups of 4-bit binary numbers; the partial product generation module calculates and outputs sixteen partial products of P30-P00, P01-P31, P32-P02 and P33-P03, wherein the P00 is a lowest bit calculation result P0; besides the P00, other fifteen partial products are respectively input into the corresponding three 4-bit carry skip adders which are cascaded in a misplaced way; the results P7-P1 can be obtained by calculating step by step, wherein P7-P0 is the calculation result output by the reversible logic-based 4-bit array multiplier. The reversible logic-based 4-bit array multiplier has the remarkable effects that a reversible logic design principle is obeyed in a design process; on the premise of guaranteeing the calculation function of a device, the circuit delay can be greatly reduced, and the energy loss can be reduced.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a digital circuit array multiplier design. Background technique [0002] With the development of integrated circuit design and technology, electronic engineers put more and more high-frequency logic components into smaller and smaller integrated circuits. At the same time, the power consumption and heating problems of logic components have attracted more and more people's attention, because these problems not only lead to waste of resources, but also cause damage to logic components due to overheating. According to Landauer's principle (Landauer's principle): any logically irreversible operation of information, every time one bit of information is erased, it will inevitably generate ln(2x*k*T) heat, k represents the Boltzmann constant, T represents the temperature . All the unnecessary heat generated in the logic components will cause energy loss, and the high temperat...

Claims

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Application Information

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IPC IPC(8): G06F7/575
Inventor 庞宇林金朝王骏超李章勇李国权周前能冉鹏
Owner CHONGQING UNIV OF POSTS & TELECOMM