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Method of forming nanowires for all-around gate devices

A technology of fully surrounded gates and nanowires, which is applied in nanotechnology, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of very high requirements for photolithography exposure patterns and dry etching capabilities, and is difficult to achieve. The effect of improving etching ability and reducing requirements

Active Publication Date: 2016-06-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In the nanowire formation process of the above-mentioned fully-enclosed gate device, because nanowires with a large arrangement density are to be formed, the distance between the nanowires will be very small, so that the photolithography exposure pattern and dry etching capability will be greatly affected in the process. The requirements are very high and difficult to achieve

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  • Method of forming nanowires for all-around gate devices
  • Method of forming nanowires for all-around gate devices
  • Method of forming nanowires for all-around gate devices

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Embodiment 1

[0058] In this embodiment, a silicon-germanium-on-insulator substrate structure is adopted, including the underlying silicon substrate (i.e., the base layer), and the oxide layer (i.e., the insulating layer) covering the substrate silicon (i.e., the insulating layer) and the insulator located on the oxide layer are oxidized and grown. Upper SiGe layer.

[0059] Si is formed by chemical vapor deposition on the above-mentioned silicon-on-insulator substrate structure 3 N 4 a nitride layer as a hard mask layer;

[0060] A patterned photoresist pattern is formed covering the Si by photolithography exposure and development. 3 N 4 on the nitride layer;

[0061] The etching process is performed to remove the area not covered by the photoresist, the etching stop layer stops on the oxide layer, and the remaining SiGe layer on insulator and Si 3 N 4 A plurality of channels formed by the nitride layer;

[0062] Epitaxially grow Si epitaxial lines at the SiGe exposed on the sidewal...

Embodiment 2

[0068] In this embodiment, a silicon-on-insulator substrate structure is adopted, including the underlying silicon substrate (i.e., the base layer), and the oxide layer (i.e., the insulating layer) covering the substrate silicon (i.e., the insulating layer) is oxidized and grown on the insulator located on the oxide layer. silicon layer.

[0069] On the above-mentioned silicon-on-insulator substrate structure by chemical vapor deposition method Si 3 N 4 a nitride layer as a hard mask layer;

[0070] A patterned photoresist pattern is formed covering the Si by photolithography exposure and development. 3 N 4 on the nitride layer;

[0071] The etching process is carried out to remove the area not covered by the photoresist, the etching stop layer stops on the oxide layer, and the remaining Si layer on the insulator and Si 3 N 4 A plurality of channels formed by the nitride layer;

[0072] Epitaxially grow SiGe epitaxial lines on the exposed Si part of the channel sidewall...

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Abstract

The invention provides a method for forming nanowires of a gate-all-around device. The method is characterized by the following steps: performing etching and forming channels, of which the arrangement density is low and space in between is large; then, growing extension lines on a semiconductor layer exposed out of the two side walls of the channels in a heteroepitaxy manner; and removing a hard mask layer, the semiconductor layer and oxide and finally forming the nanowires which are suspended corresponding to a base layer and of which the arrangement density is high. Therefore, according to the method for forming the nanowires of the gate-all-around device, the requirement for photolithography technique is effectively reduced, and etching capability is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular to a method for forming nanowires in an all-around gate device. Background technique [0002] With the continuous development of the integrated circuit industry, the critical dimensions of integrated chips are also shrinking in accordance with Moore's law, and the requirements for the device structure of integrated chips are also getting higher and higher. In advanced integrated chips, traditional planar devices have been difficult to meet the requirements of circuit design. Therefore, devices with non-planar structures have also emerged, including silicon-on-insulator, double-gate, multi-gate, nanowire field-effect transistors, and the latest three-dimensional gate. [0003] Semiconductor devices with a gate-all-around structure have the special performance of effectively limiting the short channel effect, which is what the industry is extremely eager for in the inno...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02
CPCB82Y40/00H01L21/28
Inventor 宋化龙
Owner SEMICON MFG INT (SHANGHAI) CORP