Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a first dielectric material layer is formed on a substrate, and the first dielectric material layer is located on the side wall of an initial first fin part; the first axis layer is removed; after the first axis layer is removed, etching the initial first fin part by taking the first side wall as a mask to form two first fin parts which are separated from each other and a first opening which is positioned between the two first fin parts; and after the first isolation structure is formed, the first dielectric material layer is etched back to form a second isolation structure, and the top surface of the second isolation structure is lower than the top surface of the first fin part. The first fin part and the first opening are synchronously formed by one-time etching with the first side wall as a mask, the production process is simplified, and meanwhile, the first dielectric material layer is used for forming a second isolation structure and protecting the substrate, the second fin part and the side wall of the initial first fin part from being damaged by etching.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] In the existing semiconductor field, the fin field effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has more It has strong short-channel suppression ability and stronger working current, and has been widely used in various semiconductor devices. However, with the further development of semiconductor technology, the size of transistors has been reduced to less than a few nanometers. After the size of FinFET itself has been reduced to the limit, whether it is fin distance, short channel effect, or leakage and material limitations also make transistor manufacturing at risk. , even the physical structure can't be done. [0003] Gate-all-around (GAA) devices hav...

AI Technical Summary

Problems solved by technology

However, with the further development of semiconductor technology, the scale of transistors has been reduced to below a few nanometers, and the size of FinFET itself has been reduced to the limit. Whether it is fin distance, short channel effect, or leakage and material limits, transistor manufacturing has become precarious. , even the physical structure cannot be completed

Images