High-speed A/D sampling data real-time storage method achieved based on FPGA

Abstract

The invention provides a high-speed A / D sampling data real-time storage method achieved based on an FPGA. High-speed A / D outputs four lines of 12-bit-wide differential data after sampling to send the four lines of 12-bit-wide differential data to the FPGA to carry out processing, and the data sampled by the high-speed A / D are ultimately written into two pieces of SRAMs without loss in real time after being processed through speed reduction, bit wide expansion combination, data buffering and timing sequence matching and the like in the FPGA. Through the adoption of the scheme, the problems that the data output rate of the high-speed A / D does not match with the storage rate of the SRAMs, and the output data width of the high-speed A / D does not match with the storage interface width of the SRAMs and the contradiction between the retention time of SRAM bus data and the update rate of the high-speed A / D converter data are solved effectively, the correct A / D sampling data can be stored into the SRAMs without loss in real time, and the quality of data storage is guaranteed under the situation that the system working efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of data acquisition and design, and in particular relates to a method for real-time storage of high-speed A / D sampling data realized based on FPGA. Background technique [0002] With the advancement of the large-scale integrated circuit chip manufacturing process, the sampling rate of the A / D converter in the digital sampling system is getting higher and higher with the application requirements. At present, the high-speed A / D application with a sampling rate of 1GSPS and above has become a high-sampling The method adopted by the system is difficult to implement due to the high sampling rate, such as sampling design and storage design, and there are not many applications. [0003] In the sampling system, the storage design of the sampling system with a sampling rate below 1GSPS is relatively easy to do. For example, a sampling system with a sampling rate of 200MSPS and 16-bit resolution has a data processing ...

AI Technical Summary

Problems solved by technology

[0004] However, in high-speed A / D applications with a sampling rate of 1GSPS and above, although the high-speed A / D sampler can reach a rate of 2GHz, the operating speed of the signal processing chip FPGA and the data storage chip SRAM cannot reach such a high level. It can reach 400-600MHz, and the processing rate of SRAM can reach 150-250MHz. If FPGA and SRAM are selected with a higher speed, the cost of device procurement will increase by multiples, which will greatly increase the cost of the entire acquisition system.

Images