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Semiconductor memory device

A storage device and semiconductor technology, applied in information storage, static memory, read-only memory, etc., can solve the problem of increased deletion time

Active Publication Date: 2014-03-26
KIOXIA CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With increasing capacity, the time required for erasure, especially erasure verification, increases depending on the structure of semiconductor memory devices

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0033] Each functional block can be realized by one of hardware, computer software, or a combination of both. Therefore, the description below will generally be made from the viewpoint of their functions to make it clear that each block is any one of the above. Whether such a function is performed as hardware or as software depends on design constraints on specific implementation forms or the entire system. Those skilled in the art can use various methods to realize these functions in each specific implementation form, but each implementation method is included in the category of the implementation manner. In addition, it is not necessary to distinguish each functional block as in the following specific examples. For example, some functions may be performed by other functional blocks than those illustrated in the following description. Furthermore, the illustrated functional blocks may be divided into finer functional sub-blocks. Which functional block is specified does not...

no. 2 Embodiment approach

[0084] In the first embodiment, the number of failed bits is counted for each string. On the other hand, in the second embodiment, the number of failed bits accumulated in all strings is counted.

[0085] Figure 13 It is a block diagram of the semiconductor memory device of the second embodiment. Figure 13 Based on the first embodiment ( figure 1 ),right figure 1 Several elements were added. like Figure 13 As shown, the register 15 also holds two thresholds F_BSPF and F_BSPF_ACCU, and outputs signals F_BSPF and F_BSPF_ACCU representing them respectively. The signals F_BSPF, F_BSPF_ACCU are received by the selection circuit 19 . The selection circuit 19 outputs one of the signals F_BSPF and F_BSPF_ACCU as the signal F_NF under the control of the state machine 10 . The signal F_NF is received by the verification circuit 5 as in the first embodiment. The threshold F_BSPF is the same as the threshold indicated by the signal F_NF of the first embodiment (threshold F_NF)....

no. 3 Embodiment approach

[0115] The third embodiment relates to a semiconductor storage system including the semiconductor storage device of the second embodiment and its controller.

[0116] Figure 20 A semiconductor memory system 300 according to the third embodiment is shown. like Figure 20 As shown, the semiconductor storage system 300 includes the semiconductor storage device 100 and the controller 200 according to the second embodiment. The semiconductor memory device 100 communicates with the controller 200 .

[0117] The controller 200 includes hardware and software related to the control of the semiconductor storage device 100 . The controller 200 generates a chip enable signal CEnx, a write enable signal WEnx, a read enable signal REnx, a command latch enable signal CLEx, an address latch enable signal ALEx, and a write protect signal WPnx, and supplies these to the semiconductor storage device 100. Also, the controller 200 generates signals such as addresses, commands, and data, and ...

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PUM

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Abstract

The invention provides a semiconductor memory device which is short in delete time. The semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor memory devices. Background technique [0002] For example, there is known a nonvolatile semiconductor storage device that deletes data in units of blocks. According to the structure of semiconductor memory devices, erasing, especially erasing verification time, increases with increasing capacity. Contents of the invention [0003] The present invention provides a semiconductor memory device with a short erasing time. [0004] A semiconductor memory device according to one embodiment includes a plurality of memory units (units). Each memory element includes a first transistor, a plurality of memory cell (cell) transistors, and a second transistor connected in series between first and second terminals. The control gate electrodes of the corresponding memory cell transistors in each of the plurality of memory elements are commonly connected. The bit lines are commonly connected to the firs...

Claims

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Application Information

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IPC IPC(8): G11C16/14G11C16/34
CPCG11C16/3445G11C16/16G11C16/08G11C16/10G11C16/0483G11C16/06G11C16/26G11C16/0466
Inventor 常盘直哉
Owner KIOXIA CORP
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