Automatic verification method orienting to parameterization system

An automatic verification and parameterization technology, applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of high verification cost and many verification manual participation.

Active Publication Date: 2014-04-16
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to propose an automatic verification method for parametric systems, which solves the following problems in verification of parametric systems: 1)

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  • Automatic verification method orienting to parameterization system
  • Automatic verification method orienting to parameterization system
  • Automatic verification method orienting to parameterization system

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Embodiment Construction

[0058] figure 1 It is a logical structure diagram of the parametric system automation verification framework constructed in the first step of the present invention. The entire verification framework consists of a read-in module, a true concurrent synthesis module, a model abstraction module and a verification module.

[0059] The read-in module reads in the required data from the file and the terminal, and sends it to the true concurrent synthesis module and the model abstraction module after processing. First, the read-in module reads in a single process state transition table T from an external file, and establishes a single-process LTS model M. The state transition table T describes the state transition of a single process in the form of a file, including two parts: state and transition relationship. The state transition table records the state name, action name and transition relationship, and each transition relationship is a triplet: . Each state corresponds to an ele...

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Abstract

The invention discloses an automatic verification method orienting to a parameterization system and aims at solving the problems of high verification cost, low accuracy and low speed of the parameterization system. The automatic verification method adopting the technical scheme comprises the following steps: firstly constructing an automatic verification frame of the parameterization system based on the characteristics of the parameterization system; then reading-in a single progress model, the number of progresses, properties to be verified and a user-defined predicate library from the outside, and constructing a finite-state machine model with single progress; automatically constructing a true-concurrency synthetic model with complete description of the parameterization system according to a true-concurrency synthetic rule; then automatically carrying out abstraction simplification on the true-concurrency synthetic model by adopting a predicate abstract technology to obtain an abstract model described by a finite-state machine; and finally, traversing the abstract model by adopting a model inspection technology, and judging whether the properties to be verified are met. The automatic verification method disclosed by the invention has the advantages that the cost of modeling and verification of the parameterization system can be reduced, the verification accuracy can be improved, the verification scale of the parameterization system can be reduced and the verification speed can be increased.

Description

technical field [0001] The invention relates to a model checking method in the field of formal verification, in particular to an automatic verification method oriented to a parameterized system. Background technique [0002] A parameterized system is a group of processes with the same structure and coordinated operation. The processes are executed concurrently in a synchronous or asynchronous manner. The number of processes is called a system parameter. Parameterized systems are very common in reality, such as communication protocols, Cache consistency protocols, etc. With the continuous improvement of engineering and scientific requirements, the scale of the system is expanding and the functions are becoming more and more complex, which makes the design of parametric systems very error-prone and must be verified comprehensively and effectively. Model checking technology is widely used in the field of formal verification. This method uses a finite state machine to represent...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 屈婉霞张龙郭阳李思昆汪审权胡慧俐李暾刘畅
Owner NAT UNIV OF DEFENSE TECH
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