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Synchronous memory

A memory, memory receiving technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as occupying system resources, and achieve the effect of optimizing chip area and reducing stack bit width

Active Publication Date: 2014-05-28
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since traditional memory read commands access the storage array at the fastest speed, the internal Trcd time is almost equal to the Trcd set by the external system, which will largely occupy system resources

Method used

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Examples

Experimental program
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Embodiment Construction

[0020] like figure 2 As shown, the outputs of the receiver of the read command and the receiver of the read address are connected to the data input (input) of the first-in-first-out stack, and the output of the receiver of the system clock is connected to the synchronous clock input of the first-in-first-out stack (input clock), the synchronous clock signal outputs the delayed clock signal through the digital delay phase-locked loop, as the indication signal of the first-in-first-out stack read command and the end of the address, and the indication signal is connected to the end signal input terminal of the first-in-first-out stack ( output clock); the FIFO stack outputs delayed read commands and read addresses to the storage array, and the storage array outputs parallel data.

[0021] It can be seen that in the present invention, the read command and the read address are not to access the memory array at the fastest speed, but first put it into the command address first-in-f...

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PUM

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Abstract

The invention provides a novel synchronous memory, which can save memory area and improve memory performance. The synchronous memory comprises an FIFO stack, a storage array, and a clock time lag unit, wherein the received read command and read address are both inputted into the FIFO stack; at the same time, a system clock provides a synchronous clock signal to the FIFO stack; the synchronous clock signal passes through the clock time lag unit and outputs a time lag clock signal as the index signal of reading command and end of address for the FIFO stack; the index signal is provided for the FIFO stack and the stored array respectively; the FIFO stack outputs delayed read command and read address to the storage array; the storage array outputs parallel data to enter a parallel-series-conversion module and be sent to a data output interface.

Description

Technical field: [0001] The present invention relates to a semiconductor memory. Background technique [0002] Computers and various electronic devices are widely used in all aspects of modern life, and the demand for memory products (DRAM memory) is increasing. [0003] like figure 1 As shown, the traditional memory design architecture is characterized by: the external read command and read address access the storage array at the fastest speed; the data extracted from the storage array is temporarily stored in the data first-in-first-out stack; delay( Figure 4 )) Release data from the data FIFO stack to the data output interface. [0004] There are following problems in this scheme: [0005] 1. The traditional memory architecture requires data to be first in, first out of the stack, and the general data bit width is very large, commonly 32-bit, 64-bit, or 128-bit, which occupies a large memory area. [0006] 2. The DRAM memory JEDEC standard defines the time from acti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4063
Inventor 亚历山大谈杰
Owner XI AN UNIIC SEMICON CO LTD