A Hierarchical Antenna Inspection Method for Integrated Circuit Layout Verification

Abstract

The invention discloses a layered antenna checking method of integrated circuit layout graph verification, belongs to the auxiliary design field of integrated circuit computers, and particularly relates to the field of DRC and integrated circular layout graph NE of an integrated circuit layout graph. The method comprises the basic steps that firstly, a graphic selection ascending and expression value calculation ascending method is adopted, and all layers of units are sequentially processed through an inverse topological sequence to obtain a node output conclusion; secondly, a layer result adjusting method is adopted to process all the layers of units through a topological sequence, and output nodes which are judged out are layered and optimized; finally, all the layers of units are processed through the inverse topological sequence, and a result and a layered output graph of the result are output according to existing nodes. The layered antenna checking method is utilized in the integrated circuit layout graph verification, a node expression value with the layered relation is calculated rapidly and conveniently, and the checking efficiency of an antenna is improved.

Description

technical field

[0001] The invention relates to a hierarchical antenna inspection method for integrated circuit layout verification, which belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to design rule checking (DRC) of integrated circuit layout and netlist extraction of layout and integrated circuit layout (NE) field. Background technique

[0002] With the development of integrated circuit technology, the feature size of the chip is getting smaller and smaller, the integration level of a single chip is constantly improving, the structure and process are becoming more and more complex, and the scale of the layout database is increasing exponentially. With the expansion of chip scale, the design rules that need to be verified in each stage of integrated circuit design are also increasing. Among them, the design rule checking (DRC) of the integrated circuit layout and the netlist extraction (NE) of the integrated circu...

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