A Hierarchical Antenna Inspection Method for Integrated Circuit Layout Verification

A technology of integrated circuits and inspection methods, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as reducing the yield in the production process

Active Publication Date: 2017-08-29
北京华大九天科技股份有限公司
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In layout verification, antenna inspection is a very broad class of rule inspections. The purpose of this type of inspection is to find interconnected paths with a large enough surface area. These paths may accumulate excessive charges during the manufacturing process. These paths are called for antennas, they may reduce the yield of the production process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Hierarchical Antenna Inspection Method for Integrated Circuit Layout Verification
  • A Hierarchical Antenna Inspection Method for Integrated Circuit Layout Verification
  • A Hierarchical Antenna Inspection Method for Integrated Circuit Layout Verification

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] The processing flow of this method is as follows figure 1 shown. Introduce the concrete implementation of this method below in conjunction with example, Figure 2a Shown is the layout for the example, which contains the lower cell A ( Figure 2a (1)) and the top unit Top ( Figure 2a (2)), the graphics contained in the two units involve two layers, namely layer 1 and layer 2, and the node connection relationship has been established on layer 1 and layer 2. After the connection relationship is established, the nodes constituted as contained in unit A Figure 2a (3) (4) (5) Three nodes, the unit top contains Figure 2b (6) (7) (8) (9) four nodes. The graphic position relationship information is shown in the figure. All layer 1 graphics are specified as squares with an area of ​​100 units and a perimeter of 40 units. In this example, the node expression is set as "the node whose sum of the graphic area of ​​layer 1 (denoted as area (layer 1)) is greater than 110 uni...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a layered antenna checking method of integrated circuit layout graph verification, belongs to the auxiliary design field of integrated circuit computers, and particularly relates to the field of DRC and integrated circular layout graph NE of an integrated circuit layout graph. The method comprises the basic steps that firstly, a graphic selection ascending and expression value calculation ascending method is adopted, and all layers of units are sequentially processed through an inverse topological sequence to obtain a node output conclusion; secondly, a layer result adjusting method is adopted to process all the layers of units through a topological sequence, and output nodes which are judged out are layered and optimized; finally, all the layers of units are processed through the inverse topological sequence, and a result and a layered output graph of the result are output according to existing nodes. The layered antenna checking method is utilized in the integrated circuit layout graph verification, a node expression value with the layered relation is calculated rapidly and conveniently, and the checking efficiency of an antenna is improved.

Description

technical field [0001] The invention relates to a hierarchical antenna inspection method for integrated circuit layout verification, which belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to design rule checking (DRC) of integrated circuit layout and netlist extraction of layout and integrated circuit layout (NE) field. Background technique [0002] With the development of integrated circuit technology, the feature size of the chip is getting smaller and smaller, the integration level of a single chip is constantly improving, the structure and process are becoming more and more complex, and the scale of the layout database is increasing exponentially. With the expansion of chip scale, the design rules that need to be verified in each stage of integrated circuit design are also increasing. Among them, the design rule checking (DRC) of the integrated circuit layout and the netlist extraction (NE) of the integrated circu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 张路马海南李志梁
Owner 北京华大九天科技股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap