Method for collecting etching conditions

Abstract

A method for collecting etching conditions includes the steps that wafers are divided into at least two kinds of etching areas, dielectric layers with the target thickness are formed on the wafers, after through holes are formed in the dielectric layers of the etching areas of the first kind, compensation layers are formed in the through holes and on the rest of the dielectric layers, accordingly the sum of the thickness of the compensation layers and the thickness of the rest of the dielectric layers is equal to the target thickness of the dielectric layers before the first through holes are formed, furthermore, on the premise that shapes and appearances of the through holes are not influenced, the same wafer can be etched for many times, the utilization rate of the wafers is improved, the wafers are saved, and collection cost of the etching conditions is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for collecting etching conditions. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor chips are developing towards higher integration; and the higher the integration of semiconductor chips, The feature size (Critical Dimension, referred to as CD) of the semiconductor device is smaller. The smaller feature size of semiconductor devices has brought great difficulties to the formation process of semiconductor devices, especially the etching process. [0003] When forming semiconductor devices on a wafer in the existing process, the wafer is usually first divided into several device regions, and semiconductor devices are formed in each device region under the same etching cond...

AI Technical Summary

Problems solved by technology

In the existing process, one wafer can only be used for one test, and each time the process conditions are adjusted, a new wafer needs to be provided, resulting in waste of wafers

Moreover, as the size of the wafer increases, the cost of the wafer increases, and the cost of each test increases accordingly, which is not conducive to the control of the manufacturing cost of semiconductor devices.

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