Standard cell design method resistant to single-particle latch-up effect

Abstract

A standard cell design method resistant to the single-particle latch-up effect comprises the steps that (1) trap contact protecting regions are arranged in a standard cell layout, namely areas in contact connection with traps in the standard cell layout and stretch to two sides of a transistor active area are arranged into the protecting regions, and multiple contact holes are formed in the trap contact protecting regions; (2) separation distances of the trap contact protecting regions are reduced, and the biggest separation distance (dWC) of the trap contact protecting regions is not more than 4 microns; (3) the separation distance between an NMOS and a PMOS active area is increased, and the separation distance between the NMOS and the PMOS active area is not less than 0.69 micron; (4) the distance between each trap contact protecting region and an MOS transistor source electrode is reduced, the width of a first metal layer, the width of a second metal layer and the width of a third metal layer are respectively 0.4 micron according to the design rule of the SMIC013MMRF technology, and the height of an adopted unit is 4.0 microns equivalent to the pitch widths of 10 metal layers. The method achieves reinforcing of resistance to the single-particle latch-up effect, and is low in cost, easy to implement and high in reliability.

Description

technical field [0001] The invention relates to a standard unit design method for resisting single-event latch-up effect, which belongs to CMOS integrated circuit space single-event effect protection technology. Background technique [0002] The spatial single event latch-up effect mainly appears in CMOS integrated circuits, which is caused by its internal parasitic n-p-n-p structure. The parasitic latch structure under the CMOS process is as figure 1 shown. Under the bombardment of heavy ions, a single event current will appear in the p-n junction of the well / substrate, causing a voltage drop in the well, which will cause the parasitic transistor in the latch structure (NPNP) to turn on, forming a positive feedback loop, and continuously increasing the current , eventually causing the device to be burned. [0003] At present, domestic anti-single event latch-up design and reinforcement for CMOS integrated circuits are mostly oriented to 0.18um CMOS process and adopt guar...

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Problems solved by technology

Under the bombardment of heavy ions, a single event current will appear in the p-n junction of the well / substrate, causing a voltage drop in the well, which will cause the parasitic transistor in the latch structure (NPNP) to turn on, forming a positive feedback loop, and continuously increasing the current , eventually causing the device to be burned

[0003] At present, domestic anti-single event latch-up design and reinforcement for CMOS integrated circuits are mostly oriented to 0.18um CMOS process and adopt guard ring reinforcement method. Firstly, the process size limits the working speed and scale of radiation-resistant devices, and secondly, the guard ring structure will cause layout layout. It is more difficult, greatly increasing the area of ​​the unit, parasitic capacitance, and reducing the speed of the circuit

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