Self-calibration method and device for pipeline successive comparison analog-to-digital converter

Abstract

Disclosed are a self-calibration method and device for a pipeline successive approximation type analogue to digital convertor. The self-calibration device comprises: a first-level successive approximation type analogue to digital convertor which is used for completing data acquisition and analogue to digital conversion of an input signal, wherein a pseudorandom quantity with a known digital quantity is exerted on the first-level successive approximation type analogue to digital convertor; a second-level successive approximation type analogue to digital convertor; an operational amplifier used for amplifying a residual signal output by the first-level successive approximation type analogue to digital convertor and transmitting same to the second-level successive approximation type analogue to digital convertor to conduct analogue to digital conversion; and a digital calibration control logic circuit used for conducting a cyclic calibration according to the pseudorandom quantity and the output of the first-level successive approximation type analogue to digital convertor and the second-level successive approximation type analogue to digital convertor to control the gain of the operational amplifier and obtain data output. By means of the method, the present invention can adjust the gain of an operational amplifier in real time and calibrate the influence of factors such as calibration temperature and power source voltage on the gain, thereby improving the effective accuracy of an ADC.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a self-calibration method and device for sequentially comparing analog-to-digital converters in pipelines. Background technique [0002] As the microelectronics process enters the nanoscale process, the high-speed pipeline analog-to-digital converter (Pipeline Analog to Digital Convertor, Pipeline ADC) is becoming more and more difficult to realize in the advanced nanoscale process, and because of its huge power consumption, area , is becoming increasingly unacceptable. In this context, a new technology that combines the Pipeline ADC with the Successive Approximation Register (SAR) ADC is proposed accordingly, which replaces the FLASH ADC in the single stage of the Pipeline ADC with the SAR ADC to reduce the power consumption and reduce area. Similar to the Pipeline ADC, since there is also an operational amplifier in the pipeline successive comparison analog-to-dig...

AI Technical Summary

Problems solved by technology

Therefore, under the condition that the gain and bandwidth of the operational amplifier meet the requirements, the matching degree of the operational amplifier and the capacitor determines the gain of the operational amplifier, but it puts forward higher requirements for the speed of the operational amplifier, that is, if the closed-loop amplification factor is 8, then The bandwidth of the operational amplifier needs to be 8 times of the closed-loop working bandwidth, so it has higher requirements on the working bandwidth of the operational amplifier, and it is difficult to realize that the operational amplifier needs to work at a higher bandwidth.

The open-loop-based Pipeline SAR ADC can achieve higher speed more easily, but the gain of the operational amplifier will shift with the process angle and temperature, which needs to be calibrated

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