Decoding method for LDPC coder
A decoder and decoding technology, applied in the field of termination decoding, can solve the problems of high power consumption, incomplete termination decoding conditions, high bit error rate, etc., and achieve the effect of ensuring correctness
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[0037] The logic block diagram of hardware realization of the present invention is as image 3 , the specific implementation steps are as follows: S1, the required decoding of this layer Information and verification information are taken out from the posteriori information storage module and the verification information storage module respectively, and the The sign bit is temporarily stored. S2, send the data into the operation unit to calculate and update the verification information and posteriori information S3, calculate the verification equation Hi T x and determine whether the sign bit is flipped by XOR. S4. Store the new posterior information and verification information back into the storage module. If S3 is satisfied, output the decoding result, otherwise return to S1 to start the next iteration until reaching the set maximum number of iterations.
[0038] In order to solve all check equations satisfying H T x=0, but the decoding is not necessarily completely...
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