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Variable clock DDS arbitrary waveform signal source output frequency control method and realization device

An arbitrary waveform and signal source technology, applied in the field of DDS signal source, can solve complex problems

Active Publication Date: 2014-07-23
716TH RES INST OF CHINA SHIPBUILDING INDAL CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Every time the signal frequency changes, it is often necessary to re-update the waveform data information in the waveform memory and the frequency of the sampling clock, which requires resampling when the waveform function is known or directly resampling the waveform to be simulated, so , the use of DDWS technology has certain limitations in the resolution of waveform frequency, and the generation of conventional function waveforms is more complicated than the application of DDFS technology

Method used

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  • Variable clock DDS arbitrary waveform signal source output frequency control method and realization device
  • Variable clock DDS arbitrary waveform signal source output frequency control method and realization device
  • Variable clock DDS arbitrary waveform signal source output frequency control method and realization device

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Embodiment Construction

[0050] The following will be attached Figure 5 An embodiment of the present invention will be described in detail.

[0051] This embodiment includes an upper computer, a crystal oscillator, a clock unit, a phase accumulation unit, a waveform look-up table and a DAC. The upper computer is connected to the PCI local bus through PLX9054, and the clock unit and phase accumulation unit are implemented based on FPGA (Field-Programmable Gate Array). The crystal oscillator uses a 100MHz crystal oscillator to provide a 100MHz clock for the clock unit. The waveform look-up table is realized by a 1M×16B dual-port RAM to store waveform data information. The dual-port RAM has two sets of data lines and address lines. One end realizes that the upper computer writes waveform data to the RAM through the PCI local bus, and the other end Output waveform data to the DAC.

[0052] The upper computer is connected with the clock unit, the phase accumulating unit and the dual-port RAM through the PCI...

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Abstract

The invention discloses a variable clock DDS arbitrary waveform signal source output frequency control method and a realization device. A work clock of a signal source is arranged according to the number of original waveform periodic sampling points and output frequency. Interpolation processing is performed on original waveform data according to the work clock of the signal source so that length of the original data is adjusted. The number of the sampling points in each period is adjusted by adopting a Lagrange interpolation algorithm by aiming at defects of frequency resolution in a conventional DDWS technology so that complex and variable waveforms can be generated and the requirement for resolution can be met. The method can be widely applied to the fields of automobile anti-lock braking, engine control, frequency converters, etc.

Description

Technical field [0001] The invention relates to the field of DDS signal sources, in particular to the field of a method and device for effectively controlling the output waveform frequency of an arbitrary waveform generator. Background technique [0002] Arbitrary Waveforill Generator (AWG) is a universal signal source that has developed rapidly in recent years. The arbitrary waveform generator can not only generate common signals such as sine, square wave, triangle, sawtooth, etc., but also generate arbitrary waveform sampling data through editing means, which can easily synthesize arbitrary waveform excitation signals, and has output frequency stability and high resolution. , The frequency switching speed is fast, and the output waveform phase is continuous when switching. In high-risk and high-cost experimental tests, it is possible to simulate a certain signal that is difficult to reproduce. For example, in the feasibility and stability test of the aircraft, the operation of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/02
Inventor 夏朋浩贾晓华张兴堂尹加豹朱勇张鹏吴亮王伟强王冶崔强强
Owner 716TH RES INST OF CHINA SHIPBUILDING INDAL CORP
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