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a packaging structure

A technology of packaging structure and colloid, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., to achieve the effects of good rigidity, good heat dissipation, and good thermal conductivity

Active Publication Date: 2016-08-24
日照新睿招商发展有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The traditional WLP package is packaged through wafer thinning, cutting, chipping, wire bonding, plastic packaging, ball planting, etc. With the development of technology, the memory capacity is getting larger and larger, and the packaging method has always been through stacking , to increase the memory by welding wires, and the current consumer requirements for electronic products are "small", "light" and "thin", so the way of lamination cannot meet

Method used

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Embodiment Construction

[0028] See the instructions attached figure 2 And image 3 The package structure shown in the figure is shown as a cross-sectional structure. In order to clearly display the image, no cross-sectional lines are drawn. The packaging structure shown in the figure mainly includes a metal plate 11 as a carrier, a chip 8 encapsulated on the metal plate by glue, and a solder ball 9 for external electrical connection of the chip 8.

[0029] Among them, regarding the metal plate 11, it has a first surface and a second surface opposite to the first surface. The main function of the metal plate 11 is a supporting function, which is used to support a chip or a wafer. In addition, metals generally have good thermal conductivity, which is conducive to heat dissipation. Therefore, use its good thermal conductivity to remove the heat generated by the chip during operation and improve the working performance of the chip. The other functions of the metal plate 11 are also involved in the followin...

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Abstract

The invention discloses a packaging structure, comprising: a metal plate having a first surface and a second surface opposite to the first surface; a bottom glue body attached to the first surface; a side glue body surrounding the periphery of the bottom glue body so as to be compatible with the bottom glue body The bottom colloid forms a groove structure; the chip is accommodated in the groove structure; and the solder ball is planted at a predetermined position of the chip. According to the invention, the thickness of the encapsulation is relatively small.

Description

Technical field [0001] The invention relates to a packaging structure, in particular to a WLP (Wafer level packaging, wafer level packaging, also known as wafer level packaging) structure. Background technique [0002] Wafer-level packaging is based on BGA (Ball Grid Array) technology, which is an improved and improved CSP (Chip Scale Package). In addition, the industry also refers to WLP as wafer-level-chip-scale package (WLP-CSP). [0003] Wafers and packaging technology use wafers as the processing objects. Many chips are packaged, aging, and tested at the same time on the wafers, and finally cut into individual devices, which can be directly mounted on substrates or printed circuit boards. [0004] The diffused WLP (fan-out WLP) developed in recent years, based on wafer reconfiguration technology, re-arranges the chips on an artificial wafer, and then encapsulates them according to the same steps as the standard WLP process to obtain the package area It must be larger than the ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/28
CPCH01L2224/32145H01L2224/48091H01L2224/73265H01L2924/00014
Inventor 杨怀维
Owner 日照新睿招商发展有限公司