Embedded reconfigurable system based on large-scale coarseness and processing method thereof

Abstract

The invention discloses an embedded reconfigurable system based on large-scale coarseness and a processing method of the embedded reconfigurable system. The embedded reconfigurable system comprises a system bus, a configuration bus, an embedded microprocessor, an external storage device, an interrupt controller, a direct memory access controller, an on-chip data storage device, an on-chip configuration information storage device, a reconfigurable processor and a reconfiguration controller. The method aims at an N-order FIR filter, the convolution is directly carried out on an input sequence and a filter coefficient sequence of the N-order FIR filter to obtain an output sequence, and on the basis of a direct type structure, the reconfigurable processor is used for optimization and acceleration.

Description

technical field [0001] The invention relates to the field of embedded reconfigurable systems, in particular to a large-scale coarse-grained embedded reconfigurable system and a processing method applicable to radar, communication and other occasions. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream algorithms in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is very poor. [...

AI Technical Summary

Problems solved by technology

[0005] Traditional reconfigurable computing systems such as ReMAP, AsAP, DRP and other reconfigurable system architectures, these system architecture arrays have relatively simple interconnection in the reconfigurable array, and their array utilization is low when performing FIR filter operations. Computing FIR filters, especially high-order FIR filters, has disadvantages such as a long cycle, and the interconnection between arrays does not fully consider the parallelism of FIR filtering operations, resulting in low FIR computing efficiency.

In addition, the traditional reconfigurable computing system also has a big problem in maintaining the flexibility of the order change in the FIR filtering operation and the small operation cycle.

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