Integrated passive device wafer-level packaging three-dimensional stack structure and manufacturing method

Abstract

The invention relates to an integrated passive device wafer-level packaging three-dimensional stacked structure and a manufacturing method. The integrated passive device wafer-level packaging three-dimensional stacked structure comprises a wafer-level packaging chip and an IPD chip. The IPD chip comprises a glass substrate, wherein an IPD device and a metal wiring layer are arranged on the front surface of the glass substrate, the back surface of the glass substrate is etched to form TGV holes, back surface metal wiring layers are arranged on the back surface of the glass substrate and the inner surfaces of the TGV holes, a welding ball is arranged on a welding pad of each back surface metal wiring layer, and the welding balls are connected with a PCB. The manufacturing method of the three-dimensional stacked structure comprises the following steps that (1) the wafer-level packaging chip and the IPD chip of the glass substrate are stacked; (2) the back surface of the IPD chip is etched to form the TGV holes, the back surface metal wiring layer is manufactured on the back surface of the glass substrate; (3) the back surface metal wiring layer is etched into two insulated parts; the welding pads and welding balls are manufactured on the two parts of the back surface metal wiring layer, and the welding balls are connected with the PCB. By means of the integrated passive device wafer-level packaging three-dimensional stacked structure and the manufacturing method, short-distance interconnection between the chip and the IPD device is achieved, and the electric quality is improved.

Description

technical field [0001] The invention relates to a three-dimensional stacking structure of wafer-level packaging, in particular to a three-dimensional stacking structure of wafer-level packaging of integrated passive devices and a manufacturing method thereof, belonging to the technical field of high-density electronic packaging. Background technique [0002] The difference between wafer-level packaging and traditional packaging methods is that traditional chip packaging is cut first and then packaged and tested. The area after packaging is at least 20% larger than the original chip size; while wafer-level packaging is first on the entire wafer. Carry out packaging and testing, and then dicing and segmentation. Therefore, the volume after packaging is the same as the size of the bare chip, which can greatly reduce the size of the chip after packaging. Wafer-level chip packaging provides low-cost, high-performance integrated packaging that can replace the current bonded BGA (B...

AI Technical Summary

Problems solved by technology

[0004] In the prior art, the biggest disadvantage of wafer-level chip packaging and thin-film integrated passive devices is the low degree of integration

In general, wafer-level chip packaging does not integrate passive passive devices, and the matching passive devices occupy about 80% of the circuit board area and 70% of the product assembly cost

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