NAND flash memory structure logic MTP compatible with CMOS technology

Abstract

The invention relates to an NAND flash memory structure logic MTP compatible with the CMOS technology. The NAND flash memory structure logic MTP comprises a PMOS transistor and a unit composed of an NCAP capacitor, wherein a drain electrode of the NCAP capacitor is connected with a programming line, and a floating gate of the NCAP capacitor is connected with a grid electrode of the PMOS transistor. Then, two or more units are combined together in a serial-connecting mode, and in other words, a drain electrode of each PMOS transistor is connected with a source electrode of the next PMOS transistor; the PMOS transistors which are connected in series end to end are further respectively connected with one PMOS transistor in series, substrates of all the PMOS transistors are connected together through an N trap, and substrates of all the NCAP capacitors are connected together through a P trap. The P trap can be or not be made in the deep N trap, and the P trap and a p-type substrate in the deep N trap are separated through the deep N trap. The NAND flash memory structure logic MTP compatible with the CMOS technology has the advantages that the PMOS transistors and the basic unit composed of the NCAP capacitors are connected in series so that the storage function can be achieved, connection between the source electrode and the drain electrode of each PMOS transistor can be omitted, the bit area of each basic unit is greatly reduced, and cost is reduced.

Description

technical field [0001] The invention relates to a non-volatile memory, in particular to a non-volatile memory compatible with CMOS logic technology, and belongs to the technical field of integrated circuits. Background technique [0002] For system-on-chip (SoC) applications, many blocks with different functions are integrated into one integrated circuit. Usually non-volatile memory is required to store data, ID, etc., but the usual embedded Flash requires a special process and high cost, the development cycle is long, and it is not compatible with the usual CMOS logic process. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a logic MTP with a NAND flash memory structure compatible with the CMOS process, which can reduce costs, has a small single bit area, and is fully compatible with traditional semiconductor processes and CMOS logic processes . [0004] According to the technical solut...

AI Technical Summary

Problems solved by technology

Usually non-volatile memory is required to store data, ID, etc., but the usual embedded Flash requires a special process and high cost, the development cycle is long, and it is not compatible with the usual CMOS logic process

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