System on-package multiprocessor ground-referenced single-ended interconnect

Abstract

An on-package multiprocessor ground-referenced single-ended interconnect is provided. A system of interconnected chips comprising a multi-chip module (MCM), including a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and interconnect circuitry . The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces is fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnection circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces is fabricated within the MCM package and configured to couple the second GRS interface circuit to the interconnection circuit.

Description

[0001] Statement of Rights [0002] This application was made with United States Government support under Agreement No. HR0011-10-9-0008 awarded by DARPA. The US Government has certain rights in this invention. This application is a continuation-in-part of U.S. Application Serial No. 13 / 844,570 (Attorney Docket NVIDP811 / SC-13-0072-US1), filed March 15, 2013, the entire contents of which are incorporated by reference Incorporated into this article. technical field [0003] The present invention relates to multiprocessor architectures, and more particularly, to on-package multiprocessor ground referenced single-ended interconnects. Background technique [0004] Successive generations of computing systems typically require increasing levels of performance and integration. A typical computing system includes a collection of central processing units (CPUs), graphics processing units (GPUs), high capacity memory subsystems, and interface subsystems. A collection of interface ...

AI Technical Summary

Problems solved by technology

In many cases, the die area associated with highly integrated multi-core processors is well above the feature cost knee, which results in disproportionate cost inefficiencies associated with multi-core processors

Alternatively, computing systems can be built from multiple independently packaged processing devices; however, conventional chip-to-chip signaling techniques cannot efficiently support the multiprocessing performance goals commonly associated with highly integrated multi-core devices

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