Preparation method of semiconductor device

Abstract

The invention relates to a preparation method for a semiconductor device. The preparation method includes the following steps: providing a semiconductor substrate and at least forming grid structures on the semiconductor substrate; etching the semiconductor substrate so as to form a first trench at the two sides of the grid structures; forming a barrier layer on the grid structures and the side walls of the first trench so as to form a second trench; executing wet-method etching so as to flatten the bottom part of the second trench; removing the barrier layer; and depositing a stress layer in the second trench. In the preparation method of the semiconductor device, after the first trench is formed, the barrier layer is formed on the side walls of the trench so as to form the second trench; the surface of the bottom part of the second groove is flattened so as to reduce the roughness of the horizontal plane of the bottom part of the second trench and ensure that the surface of the stress layer deposited in the follow-up process is smoother and more uniform; and therefore, the roughness of the surface of the stress layer is reduced, the deposit quality of the SiC layer is improved and the performance and yield of the device are improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for preparing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, since the semiconductor industry has advanced to the nanotechnology process node in the pursuit of high device density, high performance and low cost, especially when the size of semiconductor devices is reduced to 20nm or below, the fabrication of semiconductor devices is limited by various physical limits. [0003] In order to improve the performance of semiconductor devices in the prior art, a stress layer is introduced in the semiconductor device, and the stress layer affects the mobility of charge carriers in the device, for example, the mobility of electrons in sili...

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Problems solved by technology

The method of forming the stress layer in the prior art is illustrated by taking the SiC layer as an example. In an NMOS device, a substrate is firstly provided, and a plurality of gate structures are formed on the substrate. In the source and drain on both sides of the gate structure A trench is formed, and then the SiC stress layer is epitaxially grown in the trench, but due to the continuous reduction of semiconductor devices, after the formation of the trench, the bottom level of the trench is uneven, resulting in deposition The surface of the SiC stress layer is rough and uneven, which affects the performance of the device

[0006] Although the performance of the device can be improved through various stress layers in the prior art, when the device size drops below 20nm, the surface of the various stress layers formed becomes rough, which seriously affects the performance of the device. The key to improving device performance is to prepare a stress layer with a smooth and uniform surface at a lower size, and various means in the prior art cannot achieve the stated purpose.

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