Method and semiconductor device for single-ended edram sense amplifier

Abstract

The present application relates to methods and semiconductor devices for single-ended eDRAM sense amplifiers. More specifically, it relates to apparatus and methods for centering signal margins for single-ended eDRAM sense amplifiers. A plurality of DRAM cells are connected to the input side of the multiplexer through the first bit lines. A single-ended sense amplifier is connected to the output side of the multiplexer through a second bit line. Single-ended sense amplifiers have switching voltages. The second bit line is precharged to a selected voltage level. The multiplexer passes the signal voltage from a selected one of the plurality of DRAM cells to the second bit line. The selected voltage levels are selected such that receipt of a signal voltage of the first type adjusts the voltage of the second bit line in a first direction, and receipt of a signal voltage of the second type in a second direction opposite to the first direction Up-regulates the voltage on the second bit line so that the signal voltage is centered around the switching voltage.

Description

technical field [0001] The present disclosure relates to sensing circuits for semiconductor devices. More specifically, the present disclosure relates to semiconductor devices including voltage compensation devices to center 'high' and 'low' eDRAM bit line signal bands around the transition point of a single-ended sense amplifier. Background technique [0002] In conventional dynamic random access memory (DRAM), the sense signal from the memory cell is generated by sharing the charge stored in the memory cell with the precharged bit line charge, which then precharges the developed sense signal on the bit line. The measured signal is compared to the reference bit line. [0003] DRAM arrays generate bit line voltages that must be interpreted as 'high' or 'low' to differentiate between the digital states of '1' or '0'. Traditional differential sensing schemes use reference voltage levels that can be centered in an expected band between a '0' data voltage level and an expected...

AI Technical Summary

Problems solved by technology

[0013] Loss of centering functionality makes it difficult to design and test eDRAM arrays for high yield, maximum retention and reliability

Inability to perform true signal margin testing

Efforts to compensate for this loss of signal centering through Vdd regulation or through operating temperature limitations limit customer use and make the design uncompetitive

Tighter production controls improve eDRAM yields but increase manufacturing costs

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