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Negative Bias Temperature Instability Evaluation Method

A technology of negative bias temperature and instability, applied in the direction of electrical components, circuits, semiconductor/solid-state device testing/measurement, etc., can solve the problems of long process development cycle, increase product development cost of product development cycle, etc., and achieve shortened development Cycle time and the effect of reducing development costs

Active Publication Date: 2017-06-23
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, it directly leads to a longer process development cycle, which increases the product development cycle and product development costs.

Method used

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  • Negative Bias Temperature Instability Evaluation Method
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  • Negative Bias Temperature Instability Evaluation Method

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Embodiment Construction

[0029] The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments. It should be understood that the following examples are only used to illustrate and explain the present invention, but not to limit the technical solution of the present invention.

[0030] In the following embodiments of the present invention, real-time electrical parameters are obtained due to real-time electrical measurement of the uniformity under different interlayer dielectric layer films in the CMOS device. The interlayer dielectric layer is located between each port of the CMOS device and the metal connection layer. time; according to the measured real-time electrical parameters and the electrical parameters of the benchmark process conditions, the negative bias temperature instability of the CMOS device is evaluated. It can be seen that the negative bias temperature instability of the CMOS device can be eval...

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Abstract

The invention discloses a negative pressure temperature instability evaluation method. Due to the fact that real-time electrical measurement is conducted on uniformity of different interlayer dielectric layer thin films in a CMOS device, real-time electrical parameters are acquired, wherein interlayer dielectric layers are located between ports of the CMOS device and metal connecting layers; negative pressure temperature instability of the CMOS device is evaluated according to the measured real-time electrical parameters and electrical parameters of reference technological conditions. Thus, it can be seen that the negative pressure temperature instability of the CMOS device can be evaluated before complete wafer flow sheets are formed, so that technology and product development periods are shortened, and development cost of products is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a negative bias temperature instability evaluation method. Background technique [0002] In the process of semiconductor product development, changes in some key process conditions need to be verified by process reliability in addition to checking the results obtained through rapid electrical tests such as turn-on voltage, saturation current, resistance, and capacitance. It takes a long time to test the complete tape-out wafer in process reliability verification. Therefore, the total time required from a new process condition test to the reliability result is longer, which directly results in the extension of the development cycle. [0003] figure 1 Schematic diagram of the development process for the existing M1 etching new process in the prior art; as figure 1 As shown, for a P-type CMOS device, the process of etching a new process for the first metal laye...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/12H01L22/14
Inventor 罗飞
Owner SHANGHAI HUALI MICROELECTRONICS CORP