Multi-core CPU (Central Processing Unit) load balancing method, multi-core CPU and solid state disk

Abstract

The invention discloses a multi-core CPU (Central Processing Unit) load balancing method, a multi-core CPU and a solid state disk. The multi-core CPU comprises a front end CPU and at least one back end CPU, wherein each back end CPU is used for managing a flash memory of the solid state disk, and flash memories which are managed by different back end CPUs are different. The method comprises the steps of decomposing a read and write request from a host into sub-requests which take logical block addresses (LBA) as units by the front end CPU; obtaining the mapping relation between each sub-request and the corresponding back end CPU by the front end CPU according to the number of the back end CPUs and the number of LBAs which are contained by each flash memory page, wherein in the mapping relation, each sub-request corresponds to the unique back end CPU; sending the sub-requests to the corresponding back end CPUs by the front end CPU according to the mapping relation, and carrying out flash translation layer (FTL) processing on the sub-requests in the managed flash memories by the back end CPUs. According to the multi-core CPU load balancing method, the multi-core CPU and the solid state disk, the software design is simplified, and the development efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of data storage, in particular to a multi-core CPU load balancing method, a multi-core CPU and a solid-state hard disk. Background technique [0002] SSD (Solid State Disk) is a type of hard disk that uses flash memory as a storage medium. Compared with traditional hard disks, it has the advantages of higher speed, lower power consumption, and lower noise. [0003] Since the flash memory used in solid-state drives has a limit on the number of erasing and writing, once a certain flash memory block is erased / written for a certain number of times, data may not be written or data may be damaged. In order to avoid this situation, the solid-state hard drive introduces FTL (Flash translation layer), FTL is mapped to the PBA (Physical Block Address, Physics Block Address) of the flash memory through the LBA (Logical Block Address, Logic Block Address) of the host , to manage each physical block of the flash memory,...

AI Technical Summary

Problems solved by technology

However, in the process of processing read and write requests according to the above scheme, data sharing is likely to be performed between CPUs, that is, in many cases, communication needs to be carried out between two or more CPUs, and between CPUs Communication often requires complex algorithms, which undoubtedly increases the development cycle of load balancing code and reduces development efficiency

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