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Method and device for interconnecting chips to be verified

A to-be-verified, chip-based technology, applied in the fields of instruments, electrical digital data processing, etc., can solve the problems of reducing the efficiency and effect of multi-chip system verification, the ability to analyze signals between chips, the ability to inject delays and the poor ability to make errors, etc. To improve the ability to analyze signals between chips, improve efficiency and effect, and meet the effect of chip interconnection

Active Publication Date: 2014-10-29
INSPUR BEIJING ELECTRONICS INFORMATION IND
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Problems solved by technology

[0003] Existing methods for realizing the interconnection of chips to be verified, such as using Verilog or SystemVerilog language to realize the interconnection of chips to be verified, although the interconnection of chips to be verified can be realized, but in terms of realizing the advanced functions of the interconnection of chips to be verified, especially in the interface between chips When it is an ultra-high-speed interface (for example, an interface with a rate of more than 10Gbps), there are problems in the ability to analyze inter-chip signals and the ability to inject delays and errors in inter-chip signals, which reduces the verification of multi-chip systems. Efficiency and effectiveness cannot well meet the needs of interconnecting chips to be verified in multi-chip system verification

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  • Method and device for interconnecting chips to be verified
  • Method and device for interconnecting chips to be verified
  • Method and device for interconnecting chips to be verified

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Embodiment Construction

[0034] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0035] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0036] figure 1 For the present invention realizes the flowchart of the method for chip interconnection to be verified, each step of the method can be realized based on the SystemC language, as figure 1 As shown, the method includes the following steps: ...

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Abstract

The invention discloses a method and device for interconnecting chips to be verified. The method includes the steps that according to information formats of communication among the chips, information in multiple signals which are obtained through PLIs is analyzed to obtain an analysis result; according to preset configuration information, time delay and errors are injected into the signals which are obtained through the PLIs, and signals after injection treatment are transmitted through the PLIs; according to the analysis result and related information of the injected time delay and errors, log information is generated. According to the technical scheme, the capacity for analyzing the signals among the chips and the capacity for injecting the time delay and errors into the signals among the chips are effectively improved, so that the verifying efficiency and effect of a multi-chip system are improved, and the requirement for interconnecting the chips to be verified in the verification process of the multi-chip system is well met.

Description

technical field [0001] The invention relates to a verification technology of a multi-chip system, in particular to a method and a device for realizing interconnection of chips to be verified. Background technique [0002] With the rapid development of integrated circuit technology, simulation verification of multi-chip systems (hereinafter referred to as verification) is essential, and the verification requirements of multi-chip systems are becoming more and more complex. In this way, in the aspect of the interconnection of the chips to be verified in the verification of the multi-chip system (hereinafter referred to as the interconnection of the chips to be verified), the verification requirements of the multi-chip system not only require the realization of the interconnection of the chips to be verified, but also require the analysis of the signals between the chips. Functions such as injecting delays and errors into signals, and generating relevant log information of the ...

Claims

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Application Information

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IPC IPC(8): G06F13/28
Inventor 李拓童元满李仁刚
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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