Bearing substrate and manufacturing method thereof

A technology for carrying substrates and manufacturing methods, applied in multilayer circuit manufacturing, printed circuits connected with non-printed electrical components, electrical connection printed components, etc., can solve the problem that users cannot easily distinguish between connection pads and wiring, oxidation , affecting electrical performance and other issues, to achieve the effect of avoiding oxidation, maintaining electrical performance, and improving joint reliability

Active Publication Date: 2014-11-26
UNIMICRON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the connection pads and traces on the existing carrier substrate are on the same level, and the opening of the solder mask layer will expose the connection pads and traces in the pre-connection area at the same time
Therefore, in addition to the above-me

Method used

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  • Bearing substrate and manufacturing method thereof
  • Bearing substrate and manufacturing method thereof
  • Bearing substrate and manufacturing method thereof

Examples

Experimental program
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Example Embodiment

[0069] Figure 1A Shown is a schematic cross-sectional view of a carrier substrate according to an embodiment of the invention. Figure 1B Shown as Figure 1A The schematic top view of the circuit layer. Please refer first Figure 1A In this embodiment, the carrier substrate 100a includes a dielectric layer 110, a first circuit layer 120a, an insulating layer 130, a plurality of conductive blocks 140a, and a first conductive structure 150. In detail, the dielectric layer 110 has two opposite surfaces 112, 114 and a plurality of blind holes 116 ( Figure 1A Two are shown in the schematic). The first circuit layer 120 a is buried in the surface 112 of the dielectric layer 110 and has two surfaces 121 a and 123 a opposite to each other, wherein the surface 121 a is exposed on the surface 112 of the dielectric layer 110. The blind hole 116 extends from the surface 114 to the first circuit layer 120a and exposes a part of the surface 123a of the first circuit layer 120a. The insulating...

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Abstract

The invention discloses a bearing substrate and a manufacturing method thereof. The bearing substrate comprises a dielectric layer, a first line layer, an insulating layer, a plurality of conductive blocks and a first conductive structure. The dielectric layer has a first surface, a second surface and a plurality of blind holes. The first line layer is internally buried in the first surface, and the blind holes extend to the first line layer from the second surface. The insulating layer is arranged on the first surface and is provided with a third surface, a fourth surface and a plurality of first open holes. The first open holes expose the first line layer, and the diameter of each first open hole increases gradually from the third surface to the fourth surface. The conductive blocks are filled in the conductive blocks and are connected with the first line layer. The first conductive structure comprises a plurality of conductive holes filling to the blind holes and second line layers arranged on a part of the second surface.

Description

technical field [0001] The invention relates to a substrate and a manufacturing method thereof, and in particular to a carrier substrate suitable for carrying components and a manufacturing method thereof. Background technique [0002] In recent years, with the rapid development of electronic technology and the emergence of high-tech electronic industries, electronic products with more humanization and better functions are constantly being introduced, and are designed towards the trend of light, thin, short and small. In these electronic products, a carrier substrate is usually arranged. In addition to having conductive circuits, the carrier substrate can also carry components such as capacitors, inductors, resistors, IC chips or packages as a data processing unit of the electronic products. [0003] However, the connection pads and traces on the existing carrier substrate are on the same level, and the opening of the solder resist layer will simultaneously expose the connec...

Claims

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Application Information

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IPC IPC(8): H05K1/02H05K1/11H05K1/18H05K3/32H05K3/46
Inventor 林俊廷
Owner UNIMICRON TECH CORP
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