Manufacturing method of NOR flash cell

Abstract

The invention discloses a manufacturing method of a NOR flash cell. The manufacturing method comprises: forming a preparation etching layer including a control grid layer on an active region; performing a first etching on the preparation etching layer, then depositing a control grid protection layer, and performing a second etching on the control grid protection layer to expose a surface of the active region; filling line conductive materials in a groove with the second etching; performing a third etching to remove the line conductive materials of the predetermined position above a shallow channel insulating layer in the active region; filling interlayer dielectric (ILD) materials on the predetermined position. According to the manufacturing method of the NOR flash cell provided by the invention, damage on the control grid / floating gate protective layer (FG / CG spacer) between the line and the control grid is reduced through first filling the line conductive materials, then etching to remove the predetermined conductive materials, and then filling the ILD materials, hence higher CT-CG breakdown voltage is ensured and the NOR flash cell is not easy to be break down during the operating process of the chip.

Description

technical field [0001] The invention relates to the storage field, in particular to a method for manufacturing a NOR flash storage unit. Background technique [0002] The existing manufacturing method of the NOR Flash Cell tends to make the breakdown voltage of the connection line to the control gate (CT-CG) unstable, and it is easy to break down. At present, the manufacturing method of NOR Flash cell connection (CT) is divided into two methods: photoresist definition and control gate and control gate protective layer auxiliary definition (self-align contact). However, as the process node decreases, the distance between the control gate and the wiring of the memory cell is getting closer and closer. For example, the distance between the control gate and the wiring of 45nm NOR Flash is reduced to 30-40nm. It is difficult to achieve good insulation between the control grid and the wiring, and it is difficult to prevent breakdown within the working voltage. [0003] The manuf...

AI Technical Summary

Problems solved by technology

The key disadvantage of the existing technology is that the etching position of the ILD material is above the silicon layer (AA Si) in the active area, and the control gate protection layer will be damaged to varying degrees during etching, and then the conductive material for the wiring is filled. The conductive material of the connecting wire will be filled next to the damaged control gate protective layer, and the distance is relatively close. Therefore, when the chip is working, when the connecting wire is positively pressured and the control gate is negatively pressured, the connecting wire (source connection and drain connection) and the control gate (CT-CG) is easy to breakdown

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