Electrostatic discharge protection structure

Abstract

An electrostatic discharge protection structure comprises a semiconductor substrate, a plurality of N-type laterally-diffused field effect transistors which are in parallel arrangement on the surface of the semiconductor substrate, and a P-type body regions in the semiconductor substrate, wherein each P-type body region has a source electrode, a channel region and a body region connecting region, the body region connecting region being arranged at the outer side, close to the source electrode, of each N-type laterally-diffused field effect transistor. The drain electrode of each N-type laterally-diffused field effect transistor is connected with an electrostatic discharge input end; the source electrode of each N-type laterally-diffused field effect transistor is connected with a grounding end; the grid electrode of each N-type laterally-diffused field effect transistor is connected with a first control voltage end; and each body region connecting region is connected with a second control voltage end. The plurality of LDMOS transistors are connected together to serve as an electrostatic discharge protection structure, so that not only the electrostatic discharge capacity is improved, but also parasitic triodes can be started simultaneously, and the conduction uniformity of the electrostatic discharge protection structure is improved.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to an electrostatic discharge protection structure. Background technique [0002] As semiconductor chips are used more and more widely, the electrostatic damage involved in semiconductor chips is also more and more extensive. There are many designs and applications of electrostatic discharge protection circuits, usually including: gate grounded N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit, silicon controlled rectifier (SCR) protection circuit, lateral diffusion field Effect transistor (Laterally Diffused MOS, LDMOS) protection circuit, etc. [0003] Please refer to figure 1 , is a structural schematic diagram of an electrostatic discharge protection structure formed by using LDMOS transistors in the prior art, specifically including: a P-type substrate 10, an N-type well region 11 located in the P-type substrate 10, and an N-type well region 11 located ...

AI Technical Summary

Problems solved by technology

However, the electrostatic discharge protection structure formed by the LDMOS transistor has low electrostatic discharge capability, which makes the electrostatic protection capability poor.

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