Interference-mitigation word line driving circuit, flash memory and erasing method

Abstract

The invention discloses an interference-mitigation word line driving circuit, a flash memory and an erasing method. The word line driving circuit comprises a P type MOS transistor, a first N type MOS transistor and a second N type MOS transistor; when the flash memory is erased, a source electrode of the P type MOS transistor is floated, and moreover, during erasing, the non-erased memory cell-corresponding second N type MOS transistor is shut off to cut off electric leakage between word lines of non-erased memory cells and a negative voltage source of the word line driving circuit. With adopting of the word line driving circuit, the flash memory and the erasing method disclosed by the invention, the interference of a voltage for erasing erased memory cells in a same block to the non-erased memory cells can be mitigated, and the reliability of data erasure on the flash memory is increased.

Description

technical field [0001] The present invention relates to the technical field of semiconductor memory, and in particular, to a word line driving circuit with reduced interference, a flash memory and an erasing method. Background technique [0002] With the rapid development of microelectronic technology and computer technology, storage technology has also made great progress in recent years. Among many new storage technologies, flash storage technology has gained popularity in the market due to its non-volatility, high density, low cost and high reliability. figure 1 The cross-sectional structure of the memory cell MOS transistor of the flash memory is shown. see figure 1 , the memory cell MOS transistor includes a control gate 101 , a floating gate 102 and a substrate 103 . The memory cell MOS tube stores information by changing the number of electrons in the floating gate: when electrons are injected into the floating gate 102 of the memory cell, the threshold voltage of ...

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Problems solved by technology

In this way, for the non-erased memory cells in the same block, there will still be a certain voltage difference between the substrate and the control gate, and the stored information will be easily disturbed.

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