Manufacturing method of semiconductor package

Abstract

A semiconductor packaging part and its method, the semiconductor packaging parts include the first semiconductor chip, the second semiconductor chip, the packaging colloid, the pad, the first sub -weld, the second sub -weld, the first additional structure and the structure and the first -layer structure and the structure of the first adding layer, andThe second -layer structure, the first semiconductor chip has a relative first -effect surface and the first non -effect surface. The second semiconductor chip has a relative second effect surface and the second non -effect surface, and the second semiconductor chipThe second non -action surface is connected to the first non -action side, which is encapsulated to cover the first semiconductor chip and the second semiconductor chip.In the middle, the second electrode pad and the pads are connected, respectively, and the first -layer structure and the second -layer structure are formed on the surface.The invention can effectively reduce the plane size of the packaging parts and increase the yield.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method, especially to a semiconductor package with stacked semiconductor chips and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, semiconductor packages with different packaging types have been developed. In order to pursue the lightness, thinness and shortness of semiconductor packages, a chip scale package (CSP) technology has been developed, which is characterized in that Such chip scale packages are only equal to or slightly larger than the chip size. [0003] Figure 1A to Figure 1F The one shown is a cross-sectional view of a chip-scale package and its manufacturing method in the prior art US Pat. No. 7,202,107. [0004] Such as Figure 1A As shown, first, a carrier board 10 is provided. [0005] Such as Figure 1B As shown, then, a heat-sensitive adhesive layer 11 is formed on the carrier board 10 . [0006...

AI Technical Summary

Problems solved by technology

[0010] However, if the above-mentioned existing packages want to enhance product multitasking or functions, it is necessary to include multiple semiconductor chips in one package.

In the case where multiple semiconductor chips are placed adjacent to each other, the planar size of the package will be greatly increased; in addition, due to the thermal process and the filling process of the encapsulant (such as heating the encapsulant into a liquid and pouring it in), the semiconductor chip will Displacement occurs, and no matter whether the size of multiple semiconductor chips is the same, it is difficult to make the displacement of each semiconductor chip consistent, which will cause problems in the alignment of the subsequent line build-up process

[0011] Therefore, how to solve the problems of excessively large planar size of the package and different displacements of multiple semiconductor chips in the same package has become an urgent issue in the industry.

Images