Phase inverter, drive circuit and display panel
A technology of inverters and capacitors, applied in logic circuits, instruments, electrical components, etc., can solve problems such as unstable output signals and achieve good display effects
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Embodiment 1
[0032] Embodiment 1 of the present invention provides an inverter, and the inverter includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor; The gate of a transistor is electrically connected to the start signal input end for receiving the start signal, the source is electrically connected to the first level signal input end for receiving the first level signal, and the drain is electrically connected to the second transistor The source of the fifth transistor and the gate of the fifth transistor; the drain of the second transistor is electrically connected to the first clock signal input terminal for receiving the first clock signal through the first capacitor; the third transistor The gate of the gate is electrically connected to the second clock signal input terminal for receiving the second clock signal, the source is electrically connected to the drain of the second transistor...
Embodiment 2
[0039] Figure 2a It is a circuit diagram of an inverter provided in Embodiment 2 of the present invention. see Figure 2a , the inverter according to Embodiment 2 of the present invention includes: a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a first capacitor C1, and a second capacitor C2; The gate of a transistor MP1 is electrically connected to the initial signal input terminal IN for receiving the initial signal, the source is electrically connected to the first level signal input terminal VGH for receiving the first level signal, and the drain is electrically connected to the The source of the second transistor MP2 and the gate of the fifth transistor MP5; the gate of the second transistor MP2 is electrically connected to its drain, and the drain is used to receive the first clock signal through the first capacitor C1 The first clock signal input terminal CK is electrically connected; the gate...
Embodiment 3
[0053] this invention Figure 5a It is a circuit diagram of an inverter provided in Embodiment 3 of the present invention. see Figure 5a , the inverter according to Embodiment 3 of the present invention includes: a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a first capacitor C1, and a second capacitor C2; The gate of a transistor MP1 is electrically connected to the initial signal input terminal IN for receiving the initial signal, the source is electrically connected to the first level signal input terminal VGH for receiving the first level signal, and the drain is electrically connected to the The source of the second transistor MP2 and the gate of the fifth transistor MP5; the gate of the second transistor MP2 is electrically connected to the second level signal input terminal VGLS, and the drain passes through the first capacitor C1 It is electrically connected to the first clock signal input t...
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