A Method for Realizing Link Delay Tolerance in Enhancing Time Synchronization Process
A link delay and time synchronization technology, applied in the direction of synchronization device, time division multiplexing system, multiplexing communication, etc., can solve the problems of clock synchronization accuracy and punctuality performance, and achieve enhanced fault tolerance Performance, shorten the inspection process, improve the effect of inspection efficiency
Active Publication Date: 2018-09-14
STATE GRID CORP OF CHINA +3
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In actual situations, once the communication path is asymmetrical and jitter data occurs, if no fault-tolerant algorithm is added, it will immediately affect the timing accuracy and punctuality of clock synchronization
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[0049] Such as Figure 4 As mentioned, a method of the present invention to realize the link delay tolerance in the enhanced time synchronization process is as follows:
[0050] The link delay is assumed to be equal, so the link delay utilization (T AB +T BA ) / 2, according to the link delay under the condition that the basic network topology remains unchanged, this value is basically fixed, and the measured values with obvious differences due to the measurement of jitter can be effectively checked out by this method. Therefore, in order to ensure the punctuality and fault-tolerance rate, the Q test sampling will be performed on the measured and calculated path delay values within a certain period. The length of this period is the sampling step, and the step value is controlled and adjusted according to the value detected by sampling. If an outlier occurs, the sampling step is shortened; if no outlier occurs, the sampling step is extended. The advantage of this is that ...
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The invention relates to a method for enhancing link delay fault tolerance in the time synchronizing process. The method includes the steps that (1) a data packet of the link delay time is generated when the link transmission is computed; (2) within a certain time interval, the link delay is computed in a loop mode; (3) Q check sampling processing is conducted on the computed path delay numerical value. By means of the method, the fault tolerance of the link delay is enhanced according to an IEEE1588 protocol computing link delay method. An embedded program runs in an exchange device, no extra hardware device is needed; the jitter data are obtained effectively and scientifically through the statistical method, the step length of the sampling cycle is adjusted according to the actual conditions, and the check process is shortened, and the check efficiency is improved.
Description
technical field [0001] The invention relates to a method for realizing link delay fault tolerance, in particular to a method for realizing link delay fault tolerance in the process of enhancing time synchronization. Background technique [0002] At present, the network-based time synchronization system has a broad application space in smart substations. In the process layer communication network where time synchronization requires more precise, IEEE1588 precise network clock synchronization protocol (PTP) can meet the real-time work of its switching equipment. Require. [0003] The accuracy of the link delay is an important factor affecting the synchronization accuracy of the 1588 clock. Under ideal conditions, it is generally considered that the communication quality of the communication path is equal, that is, in the same communication path, the round-trip delay of the data packet on the link is the same. Therefore, in the 1588 protocol, the (T AB +T BA ) / 2 to calculate...
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IPC IPC(8): H04L7/00H04J3/06
Inventor 黄治王向群李春龙吴军民张刚喻强于鹏飞陈伟任杰孙晓艳黄辉黄在朝于海张增华虞跃姚启桂邓辉吴鹏王玮沈文陶静刘川陈磊黄伟
Owner STATE GRID CORP OF CHINA