All-digital naturally sampling SPWM control method and system based on FPGA

A technology of natural sampling and control method, applied in output power conversion devices, electrical components, conversion of AC power input to DC power output, etc., can solve the problems of low performance index and low switching times, and achieve fast response speed and output The effect of low harmonic content

Active Publication Date: 2015-02-04
WUHAN INSTITUTE OF TECHNOLOGY
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Problems solved by technology

In high-power applications, due to the low number of switching times, the quality of the output waveforms of the two re

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  • All-digital naturally sampling SPWM control method and system based on FPGA
  • All-digital naturally sampling SPWM control method and system based on FPGA
  • All-digital naturally sampling SPWM control method and system based on FPGA

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[0041] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention.

[0042] Taking three-level as an example, the present invention, based on the basic principles of three-level natural sampling SPWM, combined with FPGA technology, completes the calculation of the switching time of each switching device of the three-level inverter and the judgment and output of the on-off state according to the law. Control algorithm block diagram such as figure 1 Shown.

[0043] The FPGA-based fully digital three-level natural sampling SPWM control algorithm of the embodiment of the present invention, the digital functional block diagram is as follows figure 1 As shown, the digi...

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Abstract

The invention discloses an all-digital naturally sampling SPWM control method and system based on FPGA, the concrete control method comprises the steps as follows: generating the synchronizing signal; accumulating the address for the sine modulation wave to obtain the sine function value of the sine modulation wave of current region; determining the region of the current switch state according to the sine function value of the sine modulation wave and triangular carrier slope state, the sine modulation wave and triangular carrier slope are different in different regions; taking the clock signal of FPGA as the standard, fast sampling sine wave and triangular wave and comparing the value, using the counter for counting the clock signal; stopping comparing while the relationship of the sine modulation wave and triangular wave changes and recording the number of clock signal, determining the start and stop ideal value for the part according to the number of clock signal; adjusting the start and stop ideal value to obtain the actual start and stop time for realizing the symmetry dead zone.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a fully digital three-level natural sampling sinusoidal pulse width modulation (Sine pulse width modulation, SPWM) control algorithm based on Field Programmable Gate Array (Filed Programmable Gate Array, FPGA) technology. Background technique [0002] In recent years, high-power power electronic equipment has been widely used in power systems, new energy fields, and enterprise production industries. In order to improve the system output capacity and voltage level, the application of multi-level inverter circuits has become more and more in-depth. Among them, three-level The inverter circuit has been relatively maturely applied. At present, in terms of the three-level SPWM control algorithm, there are as many as 12 PWM output ports. Due to the limited number of PWM output ports of a single processor, the implementation of the processor alone cannot meet the ac...

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Application Information

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IPC IPC(8): H02M7/5395
CPCH02M7/5395
Inventor 刘健张号曾华唐伟田兮辰周尧居西子
Owner WUHAN INSTITUTE OF TECHNOLOGY
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