Manufacturing method of shallow trench isolation

A manufacturing method and shallow trench technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of uneven thickness of linear oxide layer, STI leakage, etc., and achieve better reliability and insulation. and good insulation effect

Inactive Publication Date: 2015-02-11
SEMICON MFG INT (SHANGHAI) CORP
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The present invention provides a manufacturing method of shallow trench isolation to solve the problems of the prior art that the thickness of the linear oxide layer formed on the sidewall and bottom of the trench is not uniform, and it is easy to cause STI leakage

Method used

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  • Manufacturing method of shallow trench isolation
  • Manufacturing method of shallow trench isolation
  • Manufacturing method of shallow trench isolation

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Embodiment Construction

[0029] The core idea of ​​the present invention is to provide a manufacturing method of shallow trench isolation, the manufacturing method of shallow trench isolation performs a nitrogen doping process on the trench sidewall before forming the linear oxide layer, and suppresses the formation of the trench sidewall. The thickness of the linear oxide layer is grown so that the linear oxide layer of the STI can grow uniformly on the sidewall and bottom of the trench during the growth process. In this way, it can be prevented that the linear oxide layer on the sidewall of the trench is too thick to be etched in a subsequent step, resulting in the problem that the linear oxide layer at the bottom is too thin to cause electric leakage. And after the treatment of nitrogen doping process, the reliability and insulation of STI are greatly improved.

[0030] combine image 3 , is a flowchart of a method for manufacturing shallow trench isolation according to an embodiment of the presen...

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Abstract

The invention provides a manufacturing method of a shallow trench isolation. The manufacturing method comprises the steps that a semiconductor substrate is provided, and a pad oxide layer and a nitride layer are formed on the semiconductor substrate in sequence; a trench is etched in the semiconductor substrate; a nitrogen doping process is performed on the side wall of the trench; an etching-back process is performed on the nitride layer for the first time, and the nitride layer near a part of the trench is removed; the etching-back process is performed on the oxide layer for the first time, and the pad oxide layer near a part of the trench is removed; a linear oxide layer is formed in the trench; the etching-back process is performed on the nitride layer for the second time, and the nitride layer near a part of the trench is removed; the trench is filled with a depositing medium layer. The nitrogen doping process is performed on the side wall of the trench, so that the linear oxide layer with uniform thickness can be formed, the problem of electric leakage caused by over thin linear oxide layer at the bottom due to etching for solving the problem of thick linear oxide layer on the side wall of the trench in subsequent steps is prevented, and the reliability and insulation of the STI (shallow trench isolation) are good after the nitrogen doping process is performed on the side wall of the trench.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method for shallow trench isolation. Background technique [0002] In the field of semiconductor manufacturing, shallow trench isolation (STI, shallow trench isolation) technology is widely used. In advanced flash memory technology, corner rounding is also considered in the manufacturing process of STI, making the top of STI The corners and bottom corners are rounded to reduce the impact of tip discharge on the yield of sensitive flash devices. [0003] refer to figure 1 , is a flow chart of an existing shallow trench isolation manufacturing method, specifically including the following steps: refer to Figure 2A and step S011, providing a semiconductor substrate 101, on which a pad oxide layer (pad oxide) 102 and a nitride layer (nitride layer) 103 are sequentially formed; refer to Figure 2B and step S012, etching a trench 104 on the semiconduct...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76202
Inventor 范建国沈建飞季峰强
Owner SEMICON MFG INT (SHANGHAI) CORP
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