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Bad block management system and bad block management method based on block reservation area replacement

A management system and reserved area technology, applied in the field of solid-state storage, can solve the problem that the application of the complete upper-layer FTL management algorithm is not universal, and achieve the effects of reliable performance, reduced resource consumption, and simplified process

Inactive Publication Date: 2015-02-18
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to solve the problem that the existing method uses a bad block skipping strategy, which can only be applied to the occasion of simple sequential storage operations, and does not have universal applicability for applications with complete upper-layer FTL management algorithms

Method used

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  • Bad block management system and bad block management method based on block reservation area replacement
  • Bad block management system and bad block management method based on block reservation area replacement
  • Bad block management system and bad block management method based on block reservation area replacement

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specific Embodiment approach 1

[0038] Specific implementation mode one: the following combination figure 1 , figure 2 Describe this embodiment, a kind of bad block management system based on block reserved area replacement described in this embodiment, it comprises:

[0039] A bad block management initialization module for scanning bad blocks and establishing a bad block information table;

[0040] A bad block management control module for managing bad block address mapping and bad blocks generated during operation;

[0041] The bad block information table RAM used to save the bad block information generated by the bad block management initialization module and the bad block management control module;

[0042] A hysteresis write-back module for performing data merging operations on bad blocks generated during operation;

[0043] The data merging operation is a data merging operation from the original bad block to the new good block;

[0044] After the hysteresis write-back module is performed, a module...

specific Embodiment approach 2

[0048] Specific implementation mode two: the following combination image 3 Illustrate this embodiment, what this embodiment is different from specific embodiment one is: described bad block management initialization module comprises: be used to judge whether NAND Flash is the module that starts for the first time, bad block traversal scan module, judge NAND Flash the first time A module that determines whether the data on the first page and the second page are the same;

[0049] Execute the module used to judge whether the NAND Flash is the first start-up, if so, perform bad block traversal and scan the module, otherwise, perform the module to judge whether the data on the first page and the second page of the first block of NAND Flash are the same, if so, then Carry out bad block information table import bad block information table RAM, otherwise, carry out that page data that bad block mapping information amount is big write bad block information table RAM as bad block info...

specific Embodiment approach 3

[0052] Specific implementation mode three: the following combination Figure 4 , Figure 5 This embodiment is described. The difference between this embodiment and specific embodiment 1 or 2 is that the bad block management control module includes: a module for address mapping management, and a module for managing bad blocks generated during operation;

[0053] The module for address mapping management includes: judging whether the current block is a bad block query bad block bit mark table module, query address mapping table and conversion block address output module, directly output current NAND Flash operation address module;

[0054] After the address mapping management module is turned on, it judges whether the current block is a bad block query bad block bit mark table module, if so, then inquires the address mapping table in turn and converts the block address output module, otherwise directly outputs the current NAND After Flash operates the address module, it returns...

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Abstract

The invention discloses a bad block management system and a bad block management method based on block reservation area replacement, belonging to the technical field of solid-state storage. The problem that the existing method adopts a bad block skip strategy which is only applicable to a simple sequential storage operation occasion and has no universality to an application with a complete upper-layer FTL (flash translation layer) management algorithm is solved. According to a technical scheme adopted by the invention, the bad block management method comprises the following steps: applying a bad block reservation area placement strategy to divide all blocks into a user data block area and a good block reservation area; establishing a bad block table (BBT) and a reserved translate table (RTT) based on bit index in RAM (random-access memory) in an FPGA (field programmable gate array) sheet to realize bad block identification marking and bad block mapping replacement, and forming a bad block information table by virtue of the two stables to store in NAND Flash. The bad block management system and the bad block management method disclosed by the invention can be applied to a solid-state memory (SSD).

Description

technical field [0001] The invention relates to a bad block management system and management method in the field of solid-state storage, in particular to a bad block management system and management method based on block reserved area replacement, belonging to the technical field of solid-state storage. Background technique [0002] Due to its advantages of fast access speed, low power consumption, high density, large capacity, and strong shock resistance, NAND Flash memory has been widely used in the fields of consumer electronics, computer storage systems, data acquisition, and server storage systems. In order to increase the storage capacity of SSDs and reduce its unit storage cost, NAND Flash has gradually developed from a single-level cell (Single Level Cell, SLC) to a multi-level cell (Multi-level Cell, MLC). As the size of the storage unit decreases, the reliability of NAND Flash continues to decline, and bad blocks will be generated during the production and use of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
Inventor 魏德宝邓立宝张鹏乔立岩
Owner HARBIN INST OF TECH
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