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Step type vertical gate NAND and forming method thereof

A vertical gate and ladder-type technology, which is applied in the direction of electrical components, electric solid-state devices, circuits, etc., can solve the problems that affect the expansion potential and the limitations of expansion, and achieve small correlation with the number of layers, large expansion, and few process steps Effect

Active Publication Date: 2015-03-04
TSINGHUA UNIV +1
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  • Claims
  • Application Information

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Problems solved by technology

The storage density of the BiCS structure has been greatly improved compared with the storage unit of the planar structure, but the vertical expansion of the vertical channel structure is limited, and the performance of the storage tube is related to the number of layers, which affects the its expansion potential

Method used

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  • Step type vertical gate NAND and forming method thereof
  • Step type vertical gate NAND and forming method thereof
  • Step type vertical gate NAND and forming method thereof

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Embodiment Construction

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0018] Such as figure 1 As shown, the method for forming a ladder-type vertical gate NAND according to the embodiment of the present invention may include the following steps S1 to S8:

[0019] S1. Provide a substrate and form an underlying isolation layer on the substrate, and then alternately deposit multiple layers of silicon layers and multiple layers of interlayer isolation layers on the underlying isolation layer.

[0020] Specifically, such as Figure 2a to Figure 2d As shown, SiO can be formed on a substrate 100 of Si m...

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Abstract

The invention discloses a step type vertical gate NAND with the advantages such as relatively high storage density, great development in the horizontal direction and the vertical direction. A forming method of the step type vertical grid NAND comprises the following steps of: providing a substrate, forming a bottom isolating layer, and alternatively depositing a multi-layer silicon layer and a multi-layer interlayer isolating layer; etching grooves to form a plurality of bar-shaped stacking structures, wherein each bar-shaped stacking structure is divided into a storage tube zone, a source end selecting tube zone and a tail end selecting tube zone; depositing an oxidized insulating medium on the lateral surface of each bar-shaped stacking structure, and then thinning the oxidized insulating medium of the storage tube zone; continuously depositing a silicon nitride layer and a silicon dioxide layer on the lateral surface of the storage tube region in sequence; depositing a gate electrode material and etching to form a storage tube grid electrode, a source end selecting tube grid electrode and a tail end selecting tube grid electrode; forming an apparatus source end in the source end selecting tube zone; etching step in the tail end selecting tube region to expose each silicon layer; and forming an electrode to complete electrical connection.

Description

technical field [0001] The invention belongs to the technical field of memory manufacturing, and in particular relates to a ladder type vertical gate NAND and a forming method thereof. Background technique [0002] The cost of increasing the storage density based on the planar structure is getting higher and higher, so a three-dimensional storage structure is produced. The BiCS structure and P_BiCS are 3D flash structures that have been studied extensively. The storage density of the BiCS structure has been greatly improved compared with the storage unit of the planar structure, but the vertical expansion of the vertical channel structure is limited, and the performance of the storage tube is related to the number of layers, which affects the its expansion potential. Therefore, there is an urgent need to develop new 3D memory cells. Contents of the invention [0003] The present invention aims to solve one of the technical problems in the related art at least to a certa...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L21/8247
Inventor 邓宁吴华强丰伟钱鹤
Owner TSINGHUA UNIV
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