Multi-channel FIFO (First In First Out) buffer and control method thereof

Abstract

The invention provides a multi-channel FIFO (First In First Out) buffer and a control method thereof. The FIFO buffer comprises a data storage module, a read and write pointer control module, a state identification module and a data selection module, wherein the data storage module is used for storing data and comprises an internal storage unit, an input end register array, an output end register array and a first multiplexer; the input end register array R2 comprises a plurality of input end registers; the output end register array comprises at least one output end register. A plurality of pieces of input data of a plurality of transmission channels can be transmitted at one time; after the data of the plural transmission channels is pieced to write the input end register array fully, the data is then written into an internal memory at one time, so that the problems of resource waste of the internal memory caused by wide data bit and read and write performance of the internal memory are avoided.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a multi-channel FIFO buffer and a control method thereof. Background technique [0002] FIFO (abbreviation for First In First Out in English) is a data buffer that is often used in ASIC or FPGA design, and the FIFO implements a first-in-first-out strategy during the data transfer process. FIFO buffers that implement data multi-channel / multi-data types based on FIFO generally have two structures. [0003] Among them, the implementation structure one is: using multiple FIFO buffers to respectively buffer the transmission data of multiple channels, and reading the required data from these FIFOs for corresponding processing during data processing. [0004] Such as figure 1 As shown, in this implementation manner, the number of transmission channels is 16, and the data bit width of the transmission channels is 4 bits as an example for specific description. In this way, ...

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Problems solved by technology

[0008] Such a design has restrictions on the bandwidth of data processing and the number of RAMs, and cannot be processed freely. In addition, in most data application scenarios, there will still be a waste of resources similar to the implementation method 1, so I will not go into details here.

In addition, compared with the technical solution of the realization method 1, the technical solution of the realization method 1 solves the resource waste problem that multiple dual-port RAMs must be used in multiple FIFOs, and multiple copies of read-write control and status flags generate logic, but this method has only one copy Read and write logic, it can only process data of one channel at the same time, which greatly reduces the bandwidth of data processing; further, although this method can use a small number of dual-port RAM to reduce the waste of RAM, in some cases RAM The waste of data cannot be completely prohibited. In the above example, the data bit width is 4 bits, but the minimum width of RAM in FPGA design is actually limited, and generally requires a minimum of 8 bits. In such a design, there is a 4-bit RAM. wasteful; further, this FIFO needs to add two memories R2, R3 to store read and write pointers respectively, which also leads to waste of resources; further, such a design is not flexible enough in application, and each channel occupies The storage space is relatively fixed. For example, when one or several channels have less data, the corresponding storage space cannot be effectively utilized.

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