Method for controlling data transmission between two different speed buses

Abstract

This invention discloses a control method for data transfer between two main lines with different transfer speed. It includes the following aspects: read FIFO and write FIFO for data transfer in different direction; write buffer 0 and 1 for collecting data from the write FIFO; a read buffer. The advantages of this invention are as follows: the control logic of read and write is brief; less write depth could show perfect efficiency; the write data stay in write FIFO for a short time so that the write operation can be generated earlier; data transfer can be managed with a flow style, etc.

Description

technical field [0001] The invention relates to a method for controlling data transmission between buses, in particular to a method for controlling data transmission between two buses with different speeds. Background technique [0002] In computer systems, a chip called a bridge is usually used to isolate different buses from each other. When a device on one bus wants to request resources on another bus, the bridge is responsible for converting the operation on this bus into the operation on the bus where the requested resource resides. Due to the physical and structural limitations of the bus, only a limited number of devices can be mounted on each bus. Therefore, many computer systems use multiple isolated buses in structure to provide expansion of system functions. These mutually isolated buses can use the same protocol or different protocols. The protocol conversion between different buses is done by the bridge used to isolate these buses. After the conversion of th...

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Problems solved by technology

[0004] However, the deficiency of the method in document 1 is: read FIFO and write FIFO need more complex control logic to indicate the length of valid data in FIFO, and write data needs to stay in write FIFO for a long time, in order to improve initiator bus in writing Efficiency during transmission requires a larger depth write FIFO

The method in Document 1 is not applicable when the widths of the initiator bus and the target bus are inconsistent, and Document 1 does not mention that during the read transfer, when the target bus interface writes data to the read FIFO, the initiator How to deal with the situation where the read operation is terminated

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