Method for controlling data transmission between two different speed buses

A data transmission and bus-to-bus technology, used in electrical digital data processing, instruments, etc., can solve complex, unmentioned problems, and achieve the effect of short time

Active Publication Date: 2007-03-28
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the deficiency of the method in document 1 is: read FIFO and write FIFO need more complex control logic to indicate the length of valid data in FIFO, and write data needs to stay in write FIFO for a long time, in order to improve initiator bus in writing Efficiency during transmission requires a larger depth wri

Method used

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  • Method for controlling data transmission between two different speed buses

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Embodiment Construction

[0044] The PCI (Peripheral Components Interconnect) bus is the most common and most versatile peripheral bus in current computer systems. The bridge connected to the PCI bus acts as a master (initiator) and a target (responder) on the PCI bus at the same time. On the PCI bus, the typical DMA working mode of a device is that the processor sends control commands to the device through the PCI master interface of the bridge. According to the command received, the device transmits the data to the specified area of ​​the memory through the PCI TARGET interface of the bridge or reads the data from the specified area of ​​the memory. After the data transfer is complete, the device notifies the processor to send a new command through an interrupt.

[0045] Data transmission on the PCI bus is carried out in burst mode. The target does not know the length of the current transfer until the last data of a transfer operation is transferred. The memory bus connected to the existing bridge c...

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Abstract

This invention discloses a control method for data transfer between two main lines with different transfer speed. It includes the following aspects: read FIFO and write FIFO for data transfer in different direction; write buffer 0 and 1 for collecting data from the write FIFO; a read buffer. The advantages of this invention are as follows: the control logic of read and write is brief; less write depth could show perfect efficiency; the write data stay in write FIFO for a short time so that the write operation can be generated earlier; data transfer can be managed with a flow style, etc.

Description

technical field [0001] The invention relates to a method for controlling data transmission between buses, in particular to a method for controlling data transmission between two buses with different speeds. Background technique [0002] In computer systems, a chip called a bridge is usually used to isolate different buses from each other. When a device on one bus wants to request resources on another bus, the bridge is responsible for converting the operation on this bus into the operation on the bus where the requested resource resides. Due to the physical and structural limitations of the bus, only a limited number of devices can be mounted on each bus. Therefore, many computer systems use multiple isolated buses in structure to provide expansion of system functions. These mutually isolated buses can use the same protocol or different protocols. The protocol conversion between different buses is done by the bridge used to isolate these buses. After the conversion of th...

Claims

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Application Information

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IPC IPC(8): G06F13/38
Inventor 蔡飞胡明昌曾洪博唐志敏
Owner LOONGSON TECH CORP
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